Renesas M16C Series User Manual page 61

M30240 Group
1.2.18.2.1 USB Function Interrupt
The USB Function Interrupt can be triggered by 10 sources; many of these may be cause by several different
events. Interrupt status flags associated with each source are contained in USBIS1 and USBIS2.
Endpoints 1-4 have two interrupt status flags associated with it to control data transfer or to report a STALL/
UNDER_RUN/OVER RUN condition.
The USB Endpoint x Out Interrupt Status Flag is set when
• USB FCU successfully receives a packet of data OR
• USB FCU sets the FORCE_STALL flag or OVER_RUN flag of the Endpoint x OUT CSR.
The USB Endpoint x In Interrupt Status Flag is set when
• USB FCU successfully sends a packet of data OR
• USB FCU sets the UNDER_RUN flag of the Endpoint x IN CSR.
The USB Endpoint 0 (control endpoint) has one interrupt status bit associated with it to control data transfer
or report a STALL condition.
The USB Endpoint 0 Interrupt Status Flag is set when
• USB FCU successfully receives/sends a packet of data
• Sets the SETUP_END flag or the FORCE_STALL flag, OR clears the DATA_END bit in the Endpoint 0 IN
CSR.
The Overrun/Underrun Interrupt Status Flag is set when (applicable to endpoints used for isochronous data
transfer)
• Overrun condition occurs in a endpoint (CPU is too slow to unload the data from the FIFO), OR
• Underrun condition occurs in an endpoint (CPU is too slow to load the data to the FIFO).
Each endpoint interrupt and overrun/underrun interrupt is enabled by setting the corresponding bit in the USB
Interrupt Enable Register 1 and 2.
1.2.18.2.2 USB Reset Interrupt
The USB Reset Interrupt Status Flag is set when the USB FCU sees a SE0 present on D+/D- for at least 2.5µs.
When this bit is set, all USB internal registers except INTST13 (bit5 of USBIS2) are reset to their default val-
ues. INTST13, the USB reset Interrupt Status Flag, is set to a "1" when the USB Reset is detected.
When the CPU recognizes a USB Reset Interrupt, it needs to re initialize the USB FCU so that the USB op-
eration can behave properly. It must also clear INTST13 by writing a "1" to this bit to allow a USB Reset Inter-
rupt request to occur the next time a USB Reset is detected.
Register RSTIC contains the USB Reset Interrupt's request bit and its interrupt priority select bits which are
used to enable the interrupt and set its software priority level.
1.2.18.2.3 USB Suspend and Resume Interrupts
The USB Suspend Interrupt is set when the USB FCU does not detect any bus activity on D+/D- (in J-state)
for at least 3ms.
The USB Suspend Signaling Interrupt Status Flag (INTST15, bit 7 of USBIS2) is set to a "1" when the USB
Suspend is detected. The CPU must clear INTST15 by writing a "1" to this bit to allow a USB Suspend Interrupt
request to occur the next time a USB Suspend is detected.
The USB Resume Signaling Interrupt Status Flag is set when a USB FCU is in the suspend state and detects
non-idle signaling on the D+/D-.
Register SUSPIC contains the USB Suspend Interrupt's request bit and its interrupt priority select bits which
are used to enable the interrupt and set its software priority level.
The USB Resume Interrupt request is set when the USB FCU is in the suspend state and detects non-idle
signaling on D+/D-.
The USB Signaling Interrupt Status Flag (INTST14, bit 6 of USBIS2) is set to a "1" when the USB Resume is
detected. The CPU must clear INTST14 by writing a "1" to this bit to allow a USB Resume Interrupt request
to occur the next time a USB Resume is detected.
Register RSMIC contains the USB Resume Interrupt's request bit and its interrupt priority select bits, which
are used to enable the interrupt an set its software priority level.
Rev.1.00 Sep 24, 2003 Page 43 of 360
Universal Serial Bus