Renesas M16C Series User Manual page 82

M30240 Group
Number of transfer cycles per transfer unit = Number of read cycles x j + Number of write cycles x k
Table 1.16: Number of DMAC transfer cycles
Transfer unit
8-bit transfers (DMBIT="1")
16-bit transfers (DMBIT="0")
Table 1.17: Coefficients j,k
Internal ROM/RAM No wait
1
(1) 8-bit transfers
16-bit transfers from even address and the source address is even.
Internal
clock Φ
Address
bus
Data
bus
(2) 16-bit transfers and the source address is odd
Internal
clock Φ
Address
bus
Data
bus
(3) One wait is inserted into the source read under the conditions in (1)
Internal
clock Φ
Address
bus
Data
bus
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transfferred on an 8-bit data but, there are two destination write cycles.)
Internal
clock Φ
Address
bus
Data
bus
Note : The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.57: Example of the transfer cycle for a source read
Rev.1.00 Sep 24, 2003 Page 64 of 360
Access address
Even
Odd
Even
Odd
Internal memory
Internal ROM/RAM with wait
CPU use Source Destination
CPU use Source Destination
CPU use Source Source + 1 Destination
CPU use
Source Source + 1
CPU use Source Destination
CPU use Source
CPU use Source
CPU use Source
Single-chip mode
Number of read cycles
1
1
1
2
2
CPU use
CPU use
CPU use
CPU use
Destination
CPU use
Destination CPU use
Source + 1 Destination CPU use
Source + 1 Destination
Number of write cycles
1
1
1
2
SFR area
2
CPU use
DMAC