Usb Endpoint X In Maxp Register; Usb Endpoint X Out Control & Status Register - Renesas M16C Series User Manual

M30240 Group
USB Endpoint x IN Control and Status Register
b7 b6 b5 b4
Figure 3.20: USB Endpoint x IN CSR

3.2.2.15 USB Endpoint x IN MaxP Register

This register indicates the Maximum Packet size (MaxP) of the endpoint x (x = 1-4) IN packet. This
register should be set when the SET_DESCRIPTOR command is received from the host CPU. When
the MaxP > half of FIFO size, single buffer mode is set. When the MaxP <= half of FIFO size, double
buffer mode is set.
Figure 3.21 shows the structure of the USB Endpoint x IN Maximum Packet.
USB Endpoint x IN MaxP Register
b7 b6
Figure 3.21: USB Endpoint x IN MaxP Register
3.2.2.16 USB Endpoint x OUT Control & Status Register
The USB Endpoint x OUT Control and Status Register contains the control and status information for
the specific OUT Endpoint (1-4).
• OUT_PKT_RDY Flag
This bit is set to "1" after a data packet has been successfully received from the host. This should be
cleared to "0" after data has been read from the OUT FIFO. When the AUTO_CLR bit is "1", the
OUT_PKT_RDY Flag is automatically cleared when a data packet, equal to the MaxP is unloaded.
When using double buffer mode, two or more packets of data are written to the OUT FIFO. After one
packet has been read, OUT_PKT_RDY will not become "0" even if "0" is written to the OUT_PKT_RDY
bit.
Rev.1.00 Sep 24, 2003 Page 306 of 360
b3 b2 b1 b0
Symbol
EPxICS (x=1-4)
Bit Symbol
INxCSR0
IN_PKT_RDY Flag
INxCSR1
UNDER_RUN Flag
INxCSR2 SEND_STALL Bit
INxCSR3
ISO Bit
INxCSR4
INTPT Bit
INxCSR5
TX_NOT_EPT Flag (Note 4)
INxCSR6
FLUSH Bit
INxCSR7 AUTO_SET Bit
Note 1: Write "1" only or Read
Note 2: Write "0" only or Read
Note 3: Read only
Note 4: Write only - Read "0"
Note 5: Refer to Section 1.5.5 "Programming Notes" for this register.
b5 b4 b3 b2 b1 b0
Symbol
EPxIMP (x=1-4)
Bit Symbol
IMAXP0 to
IMAXP7
Address
When reset
0319 , 0321 ,
16 16
00
0329 , 0331
16 16
Bit Name Function
0: Not ready
1: Ready
0: No FIFO underrun
1: FIFO underrun occured
0: No action
1: Stall IN Endpoint x by CPU
0: Select non-isochronous transfer
1: Select isochronous transfer
0: Select non-rate feedback interrupt transfer
1: Select rate feedback interrupt transfer
0: Transmit FIFO is empty
1: Transmit FIFO is not empty
0: No action
1: Flush FIFO
0: AUTO_SET disabled
1: AUTO_SET enabled
Address
031B , 0323 , 032B , 0333
16 16 16 16
Bit Name Function
For endpoints that support
Maximum packet size
smaller FIFO size, unused bits
(MAXP) of Endpoint x IN
are not implemented. (Always
packet
write "0" to those bits.)
Universal Serial Bus
16
R W
O O
Note 1
O O
Note 2
O O
O O
O O
O X
Note 3
O O
Note 4
O O
When reset
00
16
R W
O O