Block Diagram - Renesas M16C Series User Manual

M30240 Group

1.1.4 Block Diagram

Figure 1.2 is a block diagram of the M30240 group.
8
I/O Ports
Port P0
Internal peripheral functions
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Watchdog timer
(1 line)
DMAC
(2 channels)
Note: One serial I/O can be used for SIM interface
Figure 1.2: Block diagram of M30240 group
Rev.1.00 Sep 24, 2003 Page 4 of 360
8 8 8
Port P1 Port P2 Port P3
System clock generator
X - X
IN OUT
A-D converter
10 bits x 8 channels
USB function control unit
Frequency Synthesizer
UART/clock synchronous S I/O
(8 bits x 3 channels) Note
CRC arithemetic circuit (CCITT)
16 12
(Polynomial: X +X +X
8 8 7
Port P6 Port P7 Port P8
0
P8 , P8
6
Memory
ROM
M16C series 16-bit CPU core
Registers
R0H R0L
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
5
+1)
FLG
Block Diagram
8
~P8 , Port P8 Port P10
4
5
7
RAM
Program counter
PC
Vector table
INTB
Stack Pointer
ISP
USP
Multiplier