Renesas M16C Series User Manual page 74

M30240 Group
1.2.18.4.13 USB Endpoint 0 OUT Write Count Register
The USB Endpoint 0 OUT Write Count (WRT CNT) Register, shown in Figure 1.46, contains the number of
bytes of the current data set in the OUT FIFO. The USB FCU sets the value in the Write Count Register after
having successfully received a packet of data from the host. The CPU reads the register to determine the number
of bytes to be read from the FIFO.
USB Endpoint 0 OUT Write Count Register
b7 b6 b5 b4
0 0 0
Figure 1.46: USB Endpoint 0 OUT WRT CNT
1.2.18.4.14 USB Endpoint x IN Control and Status Register
The USB Endpoint x IN CSR (Control and Status Register), shown in Figure 1.47, contains control and status
information of the respective IN endpoint 1-4.
• INxCSR0 (IN_PKT_RDY) and INxCSR5 (TX_FIFO_NOT_EMPTY):
These two bits are for IN FIFO status when in read operation (see "IN (Transmit) FIFO" operation for details).
The CPU writes a "1" to the INxCSR0 bit to inform the USB FCU that a packet of data is written to the FIFO.
The USB FCU updates the pointers up on this bit set. The USB FCU also updates the pointers upon a packet
of data successfully sent to the host. When the pointer updates are completed, the IN FIFO status is shown
on INxCSR0 and INxCSR5 bits for the CPU to read. The CPU must allow at least one wait state between writ-
ing and reading these bits for proper FIFO status.
• INxCSR1 (UNDER_RUN):
This bit is used in ISO mode only to indicate to the CPU that a FIFO underrun has occurred. The USB FCU
sets this bit to a "1" at the beginning of an IN token if no data packet is in the FIFO. Setting this bit causes the
INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a "0" to clear this bit.
• INxCSR2 (SEND_STALL):
The CPU writes a "1" to this bit when the endpoint is stalled (transmitter halt). The USB FCU returns a STALL
handshake while this bit is set. The CPU writes a "0" to clear this bit.
• INxCSR3 (ISO/TOGGLE_INIT):
When the endpoint is used for isochronous data transfer, the CPU sets this bit to a "1" for the entire duration
of the isochronous transfer. With the ISO bit set to a "1", the device uses DATA0 as the pid for all packets sent
back to the host.
When the endpoint is required to initialize the data toggle, this set/reset of the TOGGLE_INIT bit method as-
sumes that there is no activity IN transaction to the respective endpoint on the bus at the time the initialization
process is ongoing. Set/reset of the TOGGLE_INIT bit is performed only when an endpoint experiences a con-
figuration event.
• INxCSR4 (INTPT):
The CPU writes a "1" to this bit to initialize this endpoint as a status change endpoint for IN transactions. This
bit is set only when the corresponding endpoint is to be used to communicate rate feedback information (see
Chapter. IN (Transmit) FIFOs for details).
• INxCSR5 (TX_FIFO_NOT_EPT):
The USB FCU sets this bit to a "1" when there is at least one data packet in the IN FIFO. This bit, in conjunction
with IN_PKT_RDY bit, provides the transmit IN FIFO status information (see "IN (Transmit) FIFO" for details).
• INxCSR6 (FLUSH):
Rev.1.00 Sep 24, 2003 Page 56 of 360
b3 b2 b1 b0
Symbol
EP0WC
Bit symbol
Receive byte count
W_CNT0 to
W_CNT4
Reserved
Address When reset
0315
16
Bit name Function
Must always be set to "0"
Universal Serial Bus
00
16
R W
X
X