Multiplier; Divider - Renesas M16C Series User Manual

M30240 Group

1.2.17.2 Multiplier

Clock f is a multiplied up version of clock f
VCO
and the clock input to the multiplier (f
• f = f x 2(n+1) where n is the decimal equivalent of the value loaded in FSM.
VCO PIN
Setting FSM to 255 disables the multiplier and f
Note 1: n must be chosen such that f
Note 2: Minimum f
MSB
Bit 7
7
Figure 1.25: Frequency Synthesizer Multiply Register (FSM)

1.2.17.3 Divider

Clock f is a divided down version of clock f
SYN
and the clock input to the divider (f
• f = f / 2(m+1) where m is the decimal equivalent of the value loaded in FSD.
SYN VCO
Setting FSD to 255 disables the divider and f
MSB
Bit 7
7
Figure 1.26: Frequency Synthesizer Divide Register (FSD)
Rev.1.00 Sep 24, 2003 Page 39 of 360
) from the prescaler is as follows:
PIN
equals 48 MHz.
VCO
is 1 MHz.
PIN
Bit 6 Bit 5 Bit 4
FSM
f
PIN
Dec(n)
1 MHz 23
2 MHz 11
4 MHz 5
6 MHz 3
12 MHz 1
f x 2(n+1) = f
PIN
) from the multiplier is as follows:
VCO
Bit 6 Bit 5 Bit 4
FSD
f
VCO
Dec(m) Hex(m)
48.00 MHz 1 01
48.00 MHz 127 7F
f /2(m+1) = f
VCO SYN
(See Figure 1.25). The relationship between f
PIN
= f .
VCO PIN
Bit 2
Bit 3 Bit 1
f
VCO
Hex(n)
17 48.00 MHz
0B 48.00 MHz
05 48.00 MHz
03 48.00 MHz
01 48.00 MHz
VCO
(See Figure 1.26). The relationship between f
VCO
= f .
SYN VCO
Bit 2
Bit 3 Bit 1
f
SYN
12.00 MHz
187.50 KHz
Frequency Synthesizer Circuit
Address: 03DD
16
LSB
Bit 0
Access: R/W
0
Reset: FF
16
LSB Address: 03DF
16
Bit 0
0
Access: R/W
Reset: FF
16
VCO
SYN