Renesas M16C Series User Manual page 205

M30240 Group
Example of Wiring
Example of Operation
(1) Transmission enabled
Transfer clock
"1"
Transmit
enable bit (TE)
"0"
"1"
Transmit
buffer empty
"0"
flag (Tl)
"H"
CTSi
"L"
CLKi
TxDi
Transmit register
"1"
empty flag
"0"
(TXEPT)
"1"
Transmit
interrupt request
"0"
bit (IR)
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = "0".
• Transmit interrupt cause select bit = "0".
Figure 2.45: Operation timing of transmission in clock synchronous serial I/O mode
Rev.1.00 Sep 24, 2003 Page 187 of 360
Microcomputer
CLKi
T Di
X
CTSi
(4) Transmission is complete
(2) Confirming CTS
(3) Start transmission Tc
Data is set to UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
T
CLK
Stopped pulsing because CTSi = "H"
D D D D D D D D
0 1 2 3 4 5 6 7
Cleared to "0" when interrupt request is accepted, or cleared by software
Receiver side IC
CLK
R D
X
Port
(5) Transmit next data
Stopped pulsing because
transfer enable bit = "0"
D D D D D D D D
0 1 2 3 4 5 6 7
Tc = T = 2(n + 1) / fi
CLK
fi: frequency of BRGi count source (f
n: value set to BRGi
Clock-Synchronous Serial I/O
D D D D D D D D
0 1 2 3 4 5 6 7
, f , f )
1 8 32