Renesas M16C Series User Manual page 113

M30240 Group
1.2.23.2.1 Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers con-
nected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A0
is set to "1" during reception. In this mode, the unit performs receive operation when the MSB of the received
data = "1" and does not perform receive operation when the MSB = "0".
1.2.23.2.2 Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D
mission buffer register or reading the reception buffer register. Figure 1.90 shows the example of timing for
switching serial data logic.
Example of timing for switching serial data logic when LSB is first (parity enabled, one-stop bit)
Transfer clock
TxD
2
(no reverse)
TxD
2
(reverse)
Figure 1.90: Timing for switching serial data logic
1.2.23.2.3 TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output (in-
cluding the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for usual use.
1.2.23.2.4 Bus collision detection function (UART2)
This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising edge
of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.91 shows the ex-
ample of detection timing of a buss collision (in UART mode).
Transfer clock
TxD
RxD
Bus collision detection
interrupt request signal
Bus collision detection
interrupt request bit
Figure 1.91: Detection timing of a bus collision (in UART mode)
Rev.1.00 Sep 24, 2003 Page 95 of 360
"H"
"L"
"H"
ST D0 D1 D2
"L"
"H"
ST D0 D1 D2
"L"
"H"
"L"
"H"
2 ST
"L"
"H"
2
ST
"L"
"1"
"0"
"1"
"0"
) is assigned 1, data is inverted in writing to the trans-
16
D3 D4 D5 D6 D7 P
D3 D4 D5 D6 D7 P
ST : Start bit
P : Even parity
SP : Stop bit
UART0 to UART2
, 03A8
16
SP
SP
SP
SP
ST : Start bit
SP : Stop bit
)
16