Renesas M16C Series User Manual page 76

M30240 Group
When endpoint is required to initialize the data toggle sequence bit (i.e. reset to DATA0 for the next data pack-
et), the CPU sets this bit to a "1" and then resets it to a "0" to initialize the respective endpoint's data toggle.
Successful initialization of the data toggle sequence bit can only be guaranteed if no active OUT transaction
to the respective endpoint is ongoing when the initialization process is taking place. Set/reset of the ISO/
TOGGLE_INIT bit should only be performed when an endpoint experiences a configuration event.
• OUTxCSR4 (FORCE_STALL):
The USB FCU sets this bit to a "1" when the host sends out a larger data packet than the MAXP size. The
USB FCU returns a STALL handshake while this bit is set. The CPU writes a "0" to clear this bit.
• OUTxCSR5 (DATA_ERR):
The USB FCU sets this bit to a "1" to indicate that a CRC error or a bit stuffing error was received in an ISO
packet. The CPU writes a "0" to clear this bit.
• OUTxCSR6 (FLUSH):
The CPU writes a "1" to this to flush the OUT FIFO. When there is one packet in the OUT FIFO, a flush causes
the OUT FIFO to be empty. When there are two packets in the OUT FIFO, a flush causes the older packet to
be flushed out from the OUT FIFO. Setting the OUTXCSR6 (FLUSH) bit during reception could produce un-
predictable results.
• OUTxCSR7 (AUTO_CLR):
When the CPU sets this bit to a "1", the OUT_PKT_RDY bit is cleared automatically by the USB FCU after the
number of bytes of data equal to the maximum packet size (MAXP) is unloaded from the OUT FIFO (see "OUT
(Receive) FIFO" for details).
USB Endpoint x OUT Control and Status Register (Note 3)
b7 b6 b5 b4
Figure 1.48: USB Endpoint x OUT CSR
1.2.18.4.16 USB Endpoint x IN MAXP Register
The USB Endpoint x IN MAXP Register, shown in Figure 1.49, indicates the maximum packet size (MAXP) of
an Endpoint x IN packet. The default values for Endpoints 1-4 are 0 bytes. The setting of this register also
affects the configuration of single/dual packet operation. When MAXP > 1/2 of the FIFO size, single packet
mode is set. When MAXP <= 1/2 of the FIFO size, dual packet mode is set.
USB Endpoint x IN MAXP Register
b7 b6
Figure 1.49: USB Endpoint x IN MAXP
Rev.1.00 Sep 24, 2003 Page 58 of 360
b3 b2 b1 b0
Symbol
EPiOCS (i = 1-4)
Bit symbol Bit name
OUT_PKT_RDY Flag
OUTxCSR0
OVER_RUN Flag
OUTxCSR1
SEND_STALL Bit
OUTxCSR2
ISO Bit
OUTxCSR3
FORCE-STALL Flag
OUTxCSR4
DATA-ERR Flag
OUTxCSR5
FLUSH Bit
OUTxCSR6
AUTO_CLR Bit
OUTxCSR7
Note 1: Write "0" only or read
Note 2: Write only - Read "0"
Note 3: Refer to section 1.5.5 "Programming Notes" for this register
b5 b4 b3 b2 b1 b0
Symbol
EPiIMP (i = 1-4)
Bit symbol
Maximum packet size
IMAXP0 to
(MAXP) of Endpoint x IN
IMAXP7
packet.
Address
031A 0322 032A 0332
16, 16, 16, 16
0 : Not ready
1 : Ready
0 : No FIFO overrun
1 : FIFO overrun occured
0 : No action
1 : Stall OUT Endpoint x by CPU
0 : Select non-isochronous transfer
1 : Select isochronous transfer
0 : No action
1 : Stall Endpoint X by the USB FCU
0 : No error
1 : CRC or bit stuffing error received in ISO packet
0 : No action
1 : Flush the FIFO
0 : AUTO-CLR disabled
1 : AUTO-CLR enabled
Address
031B 0323 032B 0333
16, 16, 16, 16
Function
Bit name
For endpoints that support smaller
FIFO size, unused bits are not
implemented, (always write "0" to
these bits).
Universal Serial Bus
When reset
00
16
Function R W
0 0
Note 1
0 0
Note 1
0 0
0 0
0 0
Note 1
0 0
Note 1
0 0
Note 2
0 0
When reset
00
16
R W