Renesas M16C Series User Manual page 104

M30240 Group
Table 1.25: Specifications of Clock synchronous serial I/O mode
Item
Transfer data format
Transfer clock
Transmission/reception
control
Transmission start
condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
Note 1: "n" denotes the value 00
Note 2: The UARTi receive buffer has the next data written when an overrun error occurs. Note: the UARTi receive interrupt
request bit is set to "0".
Rev.1.00 Sep 24, 2003 Page 86 of 360
•Transfer data length: 8 bits
•When internal clock is selected (bit 3 at addresses 03A0
fi/2(n+1) (Note 1) fi = f1, f8, f32
•When external clock is selected (bit 3 at addresses 03A0
Input from CLKi pin (Maximum 5 Mbps.)
CTS function/RTS function/CTS, RTS function chosen to be invalid
•To start transmission, the following requirements must be met:
Transmit enable bit (bit 0 at addresses 03A5
Transmit buffer empty flag (bit 1 at addresses 03A5
When CTS function selected, CTS input level = "L"
•Furthermore, if external clock is selected, the following requirements must also be met:
CLKi polarity select bit (bit 6 at addresses 03A4
CLKi polarity select bit (bit 6 at addresses 03A4
•
To start reception, the following requirements must be met:
Receive enable bit (bit 2 at addresses 03A5
Transmit enable bit (bit 0 at addresses 03A5
Transmit buffer empty flag (bit 1 at addresses 03A5
•
Furthermore, if external clock is selected, the following requirements must also be met:
CLKi polarity select bit (bit 6 at addresses 03A4
CLKi polarity select bit (bit 6 at addresses 03A4
•
When transmitting
Transmit interrupt cause select bit (bits 0, 1 at address 03B0
Interrupts requested when data transfer from UARTi
Transmit interrupt cause select bit (bits 0, 1 at address 03B0
Interrupts requested when data transmission from
•
When receiving
Interrupt requested when the data transfer from the UARTi receive register to the UARTi receive
buffer register is complete.
•
Overrun error (Note 2)
This error occurs when the next data is ready before contents of UARTi receive buffer is read.
•
CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be
selected
•
LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
•
Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
•
Transfer clock output from multiple pins selection (UART1)
UART1 transfer clock can be chosen by software to be output from one of the two pins set
•
Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or reading the reception buffer
register can be selected.
•
Switching serial data logic (UART2)
This function is reversing TxD port output and RxD port input. All I/O data level is reversed.
to FF that is set to the UART bit rate generator.
16 16
Specification
, 03A8 , 0378
16 16 16
, 03A8 , 0378
16 16
, 03AD , 037D ) = "1"
16 16 16
, 03AD , 037D
16 16 16
, 03AC , 037C ) = "0": CLKi input level = "H"
16 16 16
, 03AC , 037C ) = "1": CLKi input level = "L"
16 16 16
, 03AD , 037D ) = "1"
16 16 16
, 03AD , 037D = "1"
16 16 16)
, 03AD , 037D
16 16 16
, 03AC , 037C ) = "0": CLKi input level = "H"
16 16 16
, 03AC , 037C ) = "1": CLKi input level = "L"
16 16 16
, bit 4 at address 037D
16
, bit 4 at address 037D
16
UART0 to UART2
= "0"):
= "1"):
16
) = "0"
) = "0"
) = "0":
16
) = "1":
16