Renesas M16C Series User Manual page 267

M30240 Group
Table 2.36: Variation of successive comparison register and Vref while A-D converter is in progress
A-D converter stopped
1st comparison
2nd comparison
3rd comparison
8th comparison
Conversion complete
Result of A-D conversion
FF
16
FE
16
03
16
02
16
01
16
00
16
0
V
REF
x 3
2048
Figure 2.95: Theoretical A-D conversion characteristics (8-bit mode)
Rev.1.00 Sep 24, 2003 Page 249 of 360
Successive approximation register
b9
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0
n9
1st comparison result
1 0 0 0 0 0 0 0
n9 n8
2nd comparison result
n9 n8 n7 n6 n5 n4 n3
n9 n8 n7 n6 n5 n4 n3 n2
This data transfers to bit 0 and
bit 7 of A-D register
V V V
REF REF REF
x 1 x 2
256 256 256
V
b0
V
REF
[V]
2
V V
REF REF
- [V]
2 2048
V V V
REF REF
-
+
2 4 2048
V V
REF REF V
REF
+ +
2 4
V V V
REF REF REF
+ +
1 0 0
2 4
0 0
Theoretical A-D conversion
characteristic of general 8-bit
A-D converter
Theoretical A-D conversion
characteristic in the 8-bit mode
V V
REF REF
x 3 x 4 x 254
256 256
A-D Converter
change
REF
n9=1 + V
REF
4
REF
[V]
n9=0 - V
REF
4
n8=1 + V
V
REF
REF
-
[V]
8
8 2048
n8=0 - V
REF
8
V V
REF REF
+ + -
[V]
8 256 2048
V
REF
V
x 255
REF
256
Analog input voltage