Pll Auto Gear-Up And -Down (Div_G, Mul_G) - Fujitsu FR Series Application Note

Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
3.3 PLL Auto Gear-Up and –Down (DIV_G, MUL_G)
To avoid voltage drops and surges when switching the clock source from oscillator to high
frequency PLL/DLL output (or vice versa), a clock smooth gear-up and gear-down circuitry is
implemented with the PLL interface. The table below gives some recommendations. Please
check the data sheet and the hardware manual for updated values.
Main Clock SV
Cntr.
Logic
Ma in
Osci llator
1
4 MHz
0 CSVCR_
MSVE
Sub
Oscillator
Sub Clock SV
0
32 kHz
1
CSVCR_
SSVE
Cntr.
RC Logic
Oscillator
CSVCR
100 kHz
RC
0
Oscillator
1 CSCFG_
2 MHz
RCSEL
Available settings for DIV_G (PLLDIVG), MUL_G (PLLMULG):
- Main clock 4 MHz:
Name Setting DIV_G
PLLx3 0x0F
PLLx4 0x0F
PLLx5 0x0F
PLLx6 0x0F
PLLx7 0x0F
PLLx8 0x0F
PLLx9 0x0F
PLLx10 0x0F
PLLx11 0x0F
PLLx12 0x0F
PLLx13 0x0F
PLLx14 0x0F
PLLx15 0x0F
PLLx16 0x0F
PLLx17 0x0F
PLLx18 0x0F
PLLx19 0x0F
PLLx20 0x0F
PLLx21 0x0F
PLLx22 0x0F
MCU-AN-300021-E-V10
Start91460.asm
1/2
PLL Interface x1, x2, ...x25
1/G
Auto-Gear
PLL
CLKVCO
x 1/M
1/N
FB CLKPLLFB
0
Multiplier
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
CSVCR_
SCKS
Setting MUL_G
0x1F
0x1F
0x1B
0x17
0x17
0x17
0x17
0x17
0x0B
0x0B
0x0B
0x0F
0x0F
0x0F
0x0F
0x13
0x13
0x13
0x13
0x17
CLKPLL
Clock
0
1
Modulator 1
CMCR, CMPR 2
0
CMCR_ 3 CLKR_
FMOD CLKS
0
3
1 CANPRE_
CPCKS
Remark
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
- 18 - © Fujitsu Microelectronics Europe GmbH
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
Φ
Base Clock
Ext. Bus Clock
CLKT
Divider /1 .. /16
DIV1R
Peripheral Clock
CLKP
Divider /1 .. /16
DIV0R
CPU Clock
CLKB
Divider /1 .. /16
DIV0R
CAN Clock
CANCLK
Divider /1 .. /16
CANPRE