Processor Pll Voltage Supply Power Sequencing; Processor Pll Decoupling Requirements; Routing Example - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
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Figure 41. Intel Pentium

Routing Example

4.3.4.2

Processor PLL Voltage Supply Power Sequencing

Refer to Section 4.8
supply to the Intel Pentium M/Celeron M processor PLLs.
4.3.4.3

Processor PLL Decoupling Requirements

Table 20
Table 20. V
CCA[3:0]
Mid-Frequency Decoupling
High-Frequency Decoupling
NOTES:
1. VCCA[3:0] should be tied to Vcc1_8S.
2. One 10 µF and one 10 nF capacitor pair should be used for each VCCA pin.
88
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6300ESB ICH Embedded Platform Design Guide
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M/Celeron M Processor 1.8 V Intel
for more details on platform power sequencing requirements for the 1.8 V
presents the V decoupling guidelines.
CCA[3:0]
Decoupling Guidelines
Description Cap (µF)
4 x 10 µF
4 x 10 nF
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Customer Reference Board
Notes
(Polymer Covered Tantalum – POSCAP, Neocap, KO Cap)
(0603 MLCC, >= X7R)
Place next to the Intel Pentium M/Celeron M processor CPU.