Additional Host Bus Guidelines; Tck/Tms Implementation Example For Dp Designs; Single Processor Breq Strapping Requirements; Bus Request Connection Scheme For Dp Intel - Intel VC820 - Desktop Board Motherboard Design Manual

Layout/Routing Guidelines
Figure 2-41. TCK/TMS Implementation Example for DP Designs
ITP Port
Table 2-14. Bus Request Connection Scheme for DP Intel
Bus Signal
BREQ0#
BREQ1#
2.12

Additional Host Bus Guidelines

BREQ Pins
UP Systems: For uni-processor systems, the BREQ0 pin should be pulled down to ground through
a 10 Ω resistor. The BREQ1 pin should be left as a no-connect.
Figure 2-42. Single Processor BREQ Strapping Requirements
2-52
1 KΩ
R
I
non-inverting buffer
TCK
or
TMS
non-inverting buffer
Agent 0 Pins
BR0#
BR1#
BREQ0#
Vcc2.5
100 nH
motherboard trace
56 pF
100 nH
motherboard trace
56 pF
®

820 Chipset Designs

Agent 1 Pins
BR1#
BR0#
CPU #1
BREQ1#
No Connect
®
Intel 820 Chipset Design Guide
SC242
Connector A
SC242
Connector B
itp vsd