Lci (Lan Connect Interface) Guidelines; Bus Topology; Lci Routing Parameters; Point-To-Point Interconnect Guideline - Intel Pentium M Processor Design Manual

9.7.1

LCI (LAN Connect Interface) Guidelines

This section contains guidelines on how to implement a Platform LAN Connect (PLC) device on a
system motherboard using LCI. It should not be treated as a specification, and the system designer
must ensure through simulations or other techniques that the system meets the specified timings.
Special care must be given to matching the LAN_CLK traces to those of the other signals, as
shown below. The following are guidelines for the ICH3-S to LAN component interface. The
following signal lines are used on this interface:
•
LAN_CLK
•
LAN_RSTSYNC
•
LAN_RXD[2:0]
•
LAN_TXD[2:0]
This interface supports Intel
LAN_RSTSYNC, LAN_RXD0, and LAN_TXD0 are shared by all components.
9.7.1.1

Bus Topology

The LAN Connect Interface must be configured in direct point-to-point connection between the
ICH3-S and the LAN component topology (see
Figure 118.

Point-to-Point Interconnect Guideline

ICH3-S
Note: Differential pairs must be under four inches
9.7.1.2

LCI Routing Parameters

Route the LCI signals carefully on the motherboard to meet the timing and signal quality
requirements of this interface specification. The board designer should simulate the board routing
to verify that the specifications are met for flight times and skews due to trace mismatch and
crosstalk.
routing example.
Design Guide
®
Intel Pentium
®
82562ET/Intel
L = 4.5" – 10"
LAN_CLK
LAN_RSTSYNC
®
Intel
LAN_RXD[2:0]
LAN_TXD[2:0]
Table 84 presents the LCI routing parameter summary.
®
M Processor and Intel
I/O Controller Hub 3 (Intel
®
82562EM components. Signal lines LAN_CLK,
Figure 118).
®
Intel
®
Intel
®
E7501 Chipset Platform
®
ICH3-S)
82562ET
or
82562EM
Figure 119 shows the LAN_CLK
169