Troubleshooting Common Physical Layout Issues - Intel 82562EZ Design Manual

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Troubleshooting Common Physical Layout Issues

The following is a list of common physical layer design and layout mistakes in LAN On
Motherboard Designs.
1. Unequal length of the two traces within a differential pair. Inequalities create common-mode
noise and will distort the transmit or receive waveforms.
2. Lack of symmetry between the two traces within a differential pair. Asymmetry can create
common-mode noise and distort the waveforms. For each component and/or via that one trace
encounters, the other trace should encounter the same component or a via at the same distance
from the Ethernet silicon.
3. Excessive distance between the Ethernet silicon and the magnetics. Long traces on FR4
fiberglass epoxy substrate will attenuate the analog signals. In addition, any impedance
mismatch in the traces will be aggravated if they are longer than the four inch rule.
4. Routing any other trace parallel to and close to one of the differential traces. Crosstalk getting
onto the receive channel will cause degraded long cable BER. Crosstalk getting onto the
transmit channel can cause excessive EMI emissions and can cause poor transmit BER on long
cables. At a minimum, other signals should be kept 0.3 inches from the differential traces.
5. Routing one pair of differential traces too close to another pair of differential traces. After
exiting the Ethernet silicon, the trace pairs should be kept 0.3 inches or more away from the
other trace pairs. The only possible exceptions are in the vicinities where the traces enter or
exit the magnetics, the RJ-45 connector, and the Ethernet silicon.
6. Use of a low quality magnetics module.
7. Re-use of an out-of-date physical layer schematic in a Ethernet silicon design. The
terminations and decoupling can be different from one PHY to another.
8. Incorrect differential trace impedances. It is important to have ~100 Ω impedance between the
two traces within a differential pair. This becomes even more important as the differential
traces become longer. To calculate differential impedance, many impedance calculators only
multiply the single-ended impedance by two. This does not take into account edge-to-edge
capacitive coupling between the two traces. When the two traces within a differential pair are
kept close to each other, the edge coupling can lower the effective differential impedance by
5 Ω to 20 Ω. Short traces will have fewer problems if the differential impedance is slightly off
target.
9. For 82562EZ(EX) PLC designs, use of capacitor that is too large between the transmit traces
and/or too much capacitance on the magnetic module's transmit center tap to ground. Using
capacitors more than a few pF in either of these locations can slow the 100 Mbps rise and fall
time. This will also cause return loss to fail at higher frequencies and will degrade the transmit
BER performance. If a capacitor is used, it should almost certainly be less than 22 pF.
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
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