Common Physical Layout Issues - Intel Pentium 4 Design Manual

I/O Controller Hub 2
Some rules to follow that will help reduce circuit inductance in both backplanes and motherboards.
• Route traces over a continuous plane with no interruptions (do not route over a split plane).
If there are vacant areas on a ground or power plane, avoid routing signals over the vacant
area. This will increase inductance and EMI radiation levels.
• Separate noisy digital grounds from analog grounds to reduce coupling.
• Noisy digital grounds may effect sensitive DC subsystems.
• All ground vias should be connected to every ground plane; and every power via should be
connected to all power planes at equal potential. This helps reduce circuit inductance.
• Physically locate grounds between a signal path and its return. This will minimize the loop
area.
• Avoid fast rise/fall times as much as possible. Signals with fast rise and fall times contain
many high frequency harmonics , which can radiate EMI.
• The ground plane beneath the filter/transformer module should be split. The RJ45 and/or
RJ11 connector side of the transformer module should have chassis ground beneath it. By
splitting ground planes beneath transformer, noise coupling between the primary and
secondary sides of the transformer and between the adjacent coils in the transformer is
minimized. There should not be a power plane under the magnetics module.
• Create a spark gap between pins 2 through 5 of the Phoneline connector(s) and shield
ground of 1.6 mm (59.0 mil). This is a critical requirement needed to past FCC part 68 testing
for phoneline connection. Note: For worldwide certification, a trench of 2.5 mm is required.
In North America, the spacing requirements is 1.6mm. However, home networking can be
used in other parts of the world, including Europe, where some Nordic countries require the
2.5 mm spacing.
9.9.2.3

Common Physical Layout Issues

Here is a list of common physical layer design and layout mistakes in LAN On Motherboard
Designs.
1. Unequal length of the two traces within a differential pair. Inequalities create common-mode
noise and will distort the transmit or receive waveforms.
2. Lack of symmetry between the two traces within a differential pair. [Each component and/or
via that one trace encounters, the other trace must encounter the same component or a via at
the same distance from the PLC.] Asymmetry can create common-mode noise and distort the
waveforms.
3. Excessive distance between the PLC and the magnetics or between the magnetics and the
RJ-45/11 connector. Beyond a total distance of about 4 inches, it can become extremely
difficult to design a spec-compliant LAN product. Long traces on FR4 (fiberglass epoxy
substrate) will attenuate the analog signals. Also, any impedance mismatch in the traces will
be aggravated if they are longer (see #9 below). The magnetics should be as close to the
connector as possible (less than or equal to one inch).
4. Routing any other trace parallel to and close to one of the differential traces. Crosstalk getting
onto the receive channel will cause degraded long cable BER. Crosstalk getting onto the
transmit channel can cause excessive emissions (failing FCC) and can cause poor transmit
BER on long cables. At a minimum, other signals should be kept 0.3 inches from the
differential traces.
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Intel Pentium 4 Processor / Intel
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850 Chipset Family Platform Design Guide
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