1. Manuals
  2. Brands
  3. Intel Manuals
  4. Computer Hardware
  5. 80302
  6. Specification update

Intel 80302 Specification Update

I/o processor
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
®
Intel
80303 and 80302 I/O
Processors
Specification Update
May 6, 2003
®
Notice: The Intel
80303 and Intel
or errors known as errata. Characterized errata that may cause the product's behavior to deviate
from pubished specifications are documented in this specification update.
®
80302 I/O Processors processor may contain design defects
Order Number:
273355-010

Advertisement

Table of Contents
loading

Related Manuals for Intel 80302

Summary of Contents for Intel 80302

  • Page 1 ® Notice: The Intel 80303 and Intel 80302 I/O Processors processor may contain design defects or errors known as errata. Characterized errata that may cause the product’s behavior to deviate from pubished specifications are documented in this specification update. Order Number:...
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

  • Page 3: Table Of Contents

    Contents Revision History ... 5 Preface... 7 Summary Table of Changes... 8 Identification Information... 14 Errata ... 16 Specification Changes ... 23 Specification Clarifications ... 25 Documentation Changes ... 28 ® Intel 80303 and 80302 I/O Processors Specification Update...
  • Page 4 This Page Intentionally Left Blank ® Intel 80303 and 80302 I/O Processors Specification Update...

  • Page 5: Revision History

    08/22/01 04/24/01 04/02/01 03/22/01 02/23/01 08/2000 06/2000 ® Intel 80303 and 80302 I/O Processors Specification Update Description Added Errata 2. Revised Specification Clarifications 4, Reworded Specification Clarification 4. Added Specification Clarifications and 8. Added Specification Clarifications and 6. Added Document Changes and 33.

  • Page 6: Preface

    80303 I/O Processor Design Guide Nomenclature Errata are design defects or errors. These may cause the Intel Processors behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

  • Page 7: Summary Table Of Changes

    The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the...

  • Page 8: Specification Changes

    Individually Enabled by ECC Control Register Instruction Sequence Can Scoreboard a Register NoFix Indefinitely Page Status Summary of the Intel® 80302 I/O Processor Page Status ECC is Always Enabled 32-bit SDRAM is Not Supported Non-Battery Backup Systems POCCDR and SOCCDR Functionality ‘Bus Hold’...
  • Page 9 272353-001 272353-001 272353-001 272358-007 272353-001 ® Intel 80303 and 80302 I/O Processors Specification Update Page Status Documentation Changes Title Page revision number Figure 9-3 on pg 9-9 did not print correctly Figure 13-22 on pg 13-40 did not print correctly...

  • Page 10: Identification Information

    Spec Processor Number Q176 Q196 Q189 SL4Q4 SL57T Q229 SL5HS ® Intel 80303 and 80302 I/O Processors Specification Update ® Intel ® Core Notes Speed (MHz) Samples - limited testing Samples - limited testing Samples - limited testing Production Production - Yield improvement only, no functionality changes.
  • Page 11 80302 A-2 NOTE: There are no functionality differences between the A-1 and A-2 steppings of the 80303. Therefore, the Device IDs are the same. ® Intel 80303 and 80302 I/O Processors Specification Update Processor PCI-to-PCI Translation Unit Device ID Bridge Unit...

  • Page 12: Errata

    Register scoreboarding maintains register coherency by preventing parallel execution units from Problem: accessing registers for which there is an outstanding operation (see section 3.2.3 in the Intel 80303 I/O Processor Developer’s Manual). An instruction sequence that coincides with some specific instruction cache conditions can scoreboard a local or global register indefinitely.
  • Page 13 Avoid this sequence of instructions in systems that employ the instruction cache. Workaround: NoFix. Refer to Summary Table of Changes Status: ® Intel 80303 and 80302 I/O Processors Specification Update Data Type Addressing Mode • Absolute • Word - ld Displacement • Ordinal short - ldos •...

  • Page 14: Specification Changes

    Specification Changes Summary of the Intel® 80302 I/O Processor The Intel® 80302 I/O processor is based on the A-2 stepping of the Intel® 80303 I/O processor. Problem: The 80302 I/O processor is identical to the 80303 I/O processor, except the SDRAM and internal bus run at 66 MHz.

  • Page 15: Specification Clarifications

    Specification Clarifications ECC is Always Enabled ECC is always enabled, therefore do not design an Intel® 80303 I/O processor based product Problem: without ECC implemented, this causes severe system errors. On the Intel® 80960RM/RN I/O processors, ECCR.3 can be cleared to disable ECC, but with the 80303 I/O processor, ECCR.3 is reserved.
  • Page 16 (CA) and resume bit, which causes a bogus EOC. The Intel functionality is also on the 80302 since it is based on the A-2 stepping.) asserts the EOC bit when the NDAR is zero, even when the chain resume bit is set. When the resume bit is set, the CA bit is cleared for one cycle and then set again, modifying the CA and EOC at the same time.

  • Page 17: Documentation Changes

    Figure 9-3 on pg 9-9 did not print correctly. Replace Figure 9-3 with the following: Workaround: Note: "NFP" means New Frame Pointer Reserved ® Intel 80303 and 80302 I/O Processors Specification Update Fault Data FTYPE (N) Address of Faulting Instruction (n) Resumption Information Override Fault Data Fault Data...
  • Page 18 P_CLK ® Affected Docs: Intel 80303 I/O Processor Developer’s Manual. SCKE PULLCKE = 1 P_RST# I_CLK SDQ(71:0) DCLKout CLK(3:0) DCLKin ® Intel 80303 and 80302 I/O Processors Specification Update PULLCKE = 0 A6814-01 SDQ(71:0) CLK(3:0) SDRAM SDRAM DIMM0 DIMM1 A4662-02...
  • Page 19 Workaround: PCI-to-PCI Bridge ® Intel 80303 I/O Processor Developer’s Manual. Affected Docs: ® Intel 80303 and 80302 I/O Processors Specification Update Documentation Changes Primary ATU P_ORQ 16 Bytes P_OWQ 16 Bytes P_OTQ P_IWQAD P_IWQ 256 Bytes P_IRQ 256 Bytes P_ITQ1...
  • Page 20 Core Local Bus Address 1200H Default ATU Vendor ID - This is a 16-bit value assigned to Intel. This register, combined with the DID, uniquely identify the PCI device. Access type is Read/Write to allow the 80303 I/O processor to configure the 15:00...
  • Page 21 "36 (CBSC_1, "37 (CBSC_1, "38 (BC_1, "39 (CBSC_1, "40 (BC_1, "41 (CBSC_1, ® Intel 80303 and 80302 I/O Processors Specification Update Name Function Safe bit Control Signal scl, bidir, control, 1)," & sda, bidir, control, 1)," & rale, output3, 111,...
  • Page 22 111, dclk(2), output3, 111, dclk(1), output3, 111, ® Intel 80303 and 80302 I/O Processors Specification Update Disable Value Disable Result Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," &...
  • Page 23 (CBSC_1, "130 (BC_1, "131 (BC_1, "132 (CBSC_1, "133 (BC_1, "134 (CBSC_1, "135 (BC_1, ® Intel 80303 and 80302 I/O Processors Specification Update Name Function Safe bit Control Signal dclk(0), output3, 111, dclkout, output3, 111, dq(35), bidir, dq(0), bidir, control, 0)," &...
  • Page 24 201, dq(53), bidir, 204, dq(24), bidir, 201, ® Intel 80303 and 80302 I/O Processors Specification Update Disable Value Disable Result Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," &...
  • Page 25 (CBSC_1, "224 (CBSC_1, "225 (CBSC_1, "226 (CBSC_1, "227 (CBSC_1, "228 (CBSC_1, "229 (CBSC_1, ® Intel 80303 and 80302 I/O Processors Specification Update Name Function Safe bit Control Signal dq(54), bidir, 204, dq(55), bidir, 204, dq(25), bidir, 201, dq(26), bidir, 201,...
  • Page 26 0)," & s_lockz, bidir, 275, control, 0)," & s_trdyz, bidir, 280, ® Intel 80303 and 80302 I/O Processors Specification Update Disable Value Disable Result Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," &...
  • Page 27 "318 (BC_4, "319 (BC_1, "320 (BC_4, "321 (BC_1, "322 (BC_1, "323 (BC_1, ® Intel 80303 and 80302 I/O Processors Specification Update Name Function Safe bit Control Signal s_framez, bidir, 278, control, 0)," & s_devselz, bidir, 280, control, 0)," & s_irdyz,...
  • Page 28 454, p_framez, bidir, 369, control, 0)," & p_cbez(2), bidir, 453, ® Intel 80303 and 80302 I/O Processors Specification Update Disable Value Disable Result Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," &...
  • Page 29 (CBSC_1, "411 (CBSC_1, "412 (BC_1, "413 (CBSC_1, "414 (CBSC_1, "415 (CBSC_1, "416 (CBSC_1, ® Intel 80303 and 80302 I/O Processors Specification Update Name Function Safe bit Control Signal p_stopz, bidir, 373, p_trdyz, bidir, 373, control, 0)," & p_devselz bidir, 373,...
  • Page 30 0)," & control, 0)," & control, 0)," & control, 0)" ; ® Intel 80303 and 80302 I/O Processors Specification Update Disable Value Disable Result Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," & Z)," &...
  • Page 31 “It supports clock frequencies up to a maximum of 100 MHz.” ® Intel 80303 I/O Processor Developer’s Manual Affected Docs: ® Intel 80303 and 80302 I/O Processors Specification Update ® ® i960 JN CPU 100 MHz Memory 16K I-Cache Controller...
  • Page 32 Input Clock P_CLK = 33 MHz P_CLK = 66 MHz P_CLK = 66 MHz NOTE: Combination of P_M66EN=0 and S_M66EN=1 is not supported by the Intel When P_M66EN=0, the 80303 I/O processor forces S_M66EN=0 ensuring the unsupported condition never occurs. ®...
  • Page 33 Intel 80303 I/O Processor Developer’s Manual Affected Docs: ® Intel 80303 and 80302 I/O Processors Specification Update 100 MHz Intel i960 Processor Local Bus ® 100 MHz Internal Bus (IB) Special Downstream Window Enable - When set, a special downstream memory window which includes the addresses FEC0_0000h through FECF_FFFFh is opened.
  • Page 34 Change the last paragraph to the following: 'Note that bits 4:0, 11, 9 and 7 can result in an NMI# Workaround: interrupt driven to the i960 core processor.' ® Intel 80303 I/O Processor Developer’s Manual Affected Docs: ® Intel 80303 and 80302 I/O Processors Specification Update...
  • Page 35 <= 115 ns <= 175 ns ® Affected Docs: Intel 80303 I/O Processor Developer’s Manual ® Intel 80303 and 80302 I/O Processors Specification Update Attribute Legend: RV = Reserved PR = Preserved RS = Read/Set Description Address-to-Data Wait States Documentation Changes...
  • Page 36 Affected Docs: Symptom Main Memory Calculate ECC with G-matrix Calculate Syndrome by Comparing ECC w/Check Bits Data Corrector Error Type/Location (single-bit error) Data to Internal Bus ® Intel 80303 and 80302 I/O Processors Specification Update Memory H-matrix Look-up Table A8160-01...
  • Page 37 80303 I/O Processor Developer’s Manual Affected Docs: Section 11.3.1.5 FAIL# Code The verbiage in this section is residual from the Intel Problem: where the internal bus was accessible from the outside. The internal bus is not accessible from the outside for i960 RM/RN I/O processor. Since the customer cannot “see” the internal bus, whatever is on it is not useful and is only confusing.
  • Page 38 Section 4.5.2 on page 50 is only correct for A-0 and A-1 steppings The second sentence in Note 7 states, ‘S_REQ64# is deasserted one P_CLK after the deassertion of Problem: S_RST#’. This statement is not correct for the A-2 stepping of the 80303 and 80302 I/O processors. Workaround: This statement is only correct for the A-0 and A-1 steppings of the 80303.

This manual is also suitable for:

80303

Table of Contents