Esd; Ioapic (I/O Advanced Programmable Interrupt Controller) - Intel 852GM Design Manual

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Finding a common mode choke that meets the designer's needs is a two-step process. A part must be
chosen with the impedance value that provides the required noise attenuation. This is a function of the
electrical and mechanical characteristics of the part chosen and the frequency and strength of the noise
present on the USB traces that you are trying to suppress.
Once you have a part that gives passing EMI results, the second step is to test the effect this part has on
signal quality. Higher impedance common-mode chokes generally have a greater damaging effect on
signal quality, so care must be used when increasing the impedance without doing thorough testing.
Thorough testing means that the signal quality must be checked for Low-speed, Full-speed, and High-
speed USB operation.
10.4.5.

ESD

Classic USB (1.0/1.1) provided ESD suppression using in line ferrites and capacitors forms a low pass
filter. This technique doesn't work for USB 2.0 due to the much higher signal rate of high-speed data. A
device that has been tested successfully is based on spark gap technology. Proper placement of any ESD
protection device is on the data lines between the common-mode choke and the USB connector data pins
as shown in Figure 84. Other types of low-capacitance ESD protection devices may work as well but
were not investigated. As with the common mode choke solution, it is recommended to include
footprints for some type of ESD protection device as a stuffing option in case it is needed to pass ESD
testing.
10.5. IOAPIC (I/O Advanced Programmable Interrupt
Controller)
On a Mobile Intel Pentium 4 Processor-M, mobile Intel Celeron Processor and Intel Celeron M
Processor based platforms, the serial IOAPIC bus interface of the Intel ICH4-M should be disabled.
IOAPIC is supported on the platform and the servicing of interrupts is accomplished via a processor
Front Side Bus interrupt delivery mechanism.
IOxAPIC is enabled by setting DT bit, xAPIC and APIC_EN bit, BIOS needs to program these bits
when IOxAPIC is enabled.
The IOxAPIC only use FSB as a medium of message transfer so grounding PICD[1:0] and PICCLK
will not have any effect on FSB interrupt delivery and it will only affect serial APIC transfer.
The serial IOAPIC bus interface of the Intel ICH4-M should be disabled as follows.
• Tie APICCLK directly to ground
• Tie PICD0, PICD1 to ground through a 10-kΩ resistor (separate pull-downs are required if using
XOR chain testing)
The Mobile Intel Pentium 4 processor- M, mobile Intel Celeron processor and Intel Celeron M
processors do not have pins dedicated for an IOAPIC bus interface and no hardware change is
necessary.
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Intel 852GM Chipset Platform Design Guide
I/O Subsystem
169