Storing Masked Interrupts; Serial Video Rx Interrupts; Introduction - Analog Devices ADV8003 Hardware Manual

Function
intrq_dur_sel[1:0]
00 
01
10
11
Note: When the active until cleared interrupt duration is selected and the event that caused an interrupt ends, the interrupt persists until
it is cleared or masked.
9.1.2.

Storing Masked Interrupts

store_unmasked_irqs, IO Map, Address 0x1A69[7]
This bit is used to specify whether the HDMI status flags for any HDMI interrupt should be triggered regardless of whether the mask
bits are set. This bit allows an HDMI interrupt to trigger and allows this interrupt to be read back through the corresponding status bit
without triggering an interrupt on the interrupt pin. The status is stored until the clear bit is used to clear the status register and allows
another interrupt to occur.
Function
store_unmasked_irqs
0 
1

9.2. SERIAL VIDEO RX INTERRUPTS

9.2.1.

Introduction

This section describes the interrupt support provided for the Serial Video Rx on the ADV8003. The Serial Video Rx interrupts are OR' d
together and connected to the ADV8003 INT2 pin.
The ADV8003 Serial Video Rx interrupt architecture provides the following types of bits:
•
Raw bits
• Status bits
• Interrupt mask bits
• Clear bits
Raw bits are defined as being either edge-sensitive or level-sensitive. The following compares an edge-sensitive interrupt and a level-
sensitive interrupt to demonstrate the difference.
level_sensitive_int_raw, IO, Address 0xXX (Read Only)
This readback indicates the raw status of the level sensitive interrupt. This bit is set to one when a condition occurs and is reset to 0
when the condition is no longer apparent.
Function
level_sensitive_int_raw
0 
1
Rev. B, August 2013
Description
4 Xtal periods
16 Xtal periods
64 Xtal periods
Active until cleared
Description
Do not store triggered interrupts
Store triggered interrupts
Description
Event/condition not currently occuring
Event/condition currently occurring
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ADV8003 Hardware Manual