Receive Buffers - Analog Devices ADV8003 Hardware Manual

Video signal processor with motion adaptive deinterlacing, scaling, bitmap osd, dual hdmi tx and video encoder
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logical_address0[3:0]
if
logical_address_mask[2:0]
logical_address2[3:0], TX2 CEC Map, Address 0xF84D[3:0]
This signal is used to specify logical address 2. This address must be enabled by setting CEC_LOGICAL_ADDRESS_MASK[2] to 1.
Function
logical_address2[3:0]
1111 
xxxx
logical_address1[3:0], TX2 CEC Map, Address 0xF84C[7:4]
This signal is used to specify logical address 1. This address must be enabled by setting CEC_LOGICAL_ADDRESS_MASK[1] to 1.
Function
logical_address1[3:0]
1111 
xxxx
logical_address0[3:0], TX2 CEC Map, Address 0xF84C[3:0]
This signal is used to specify logical address 0. This address must be enabled by setting CEC_LOGICAL_ADDRESS_MASK[0] to 1.
Function
logical_address0[3:0]
1111 
xxxx
logical_address_mask[2:0], TX2 CEC Map, Address 0xF84B[6:4]
This signal is used to specify the logical address mask of the CEC logical devices, support up to 3 logical devices. When the bit is one, the
related logical device will be enabled, and the messages whose destination address is matched with the logical address will be accepted.
Function
logical_address_mask[2
:0]
001 
010
100
7.3.2.

Receive Buffers

The ADV8003 features three frame buffers which allow the Rx to receive up to three messages before the host processor needs to read a
message out. When three messages are received, no further message reception is possible until the host reads at least one message.
For backwards compatibility with previous generation ADI CEC-enabled parts, only one frame buffer is enabled by default. In this default
mode, after a message is received, the host processor must read the message out before any further message reception is possible. The
decision to use one or three messages buffers is controlled by the
use_all_bufs, TX2 CEC Map, Address 0xF84A[3]
This bit is used to select whether the new frames should be received in all three buffers or only one buffer.
Rev. B, August 2013
is set to 001
Description
Default value
User specified logical address
Description
Default value
User specified logical address
Description
Default value
User specified logical address
Description
Use logical_address0 for CEC controller
Use logical_address1 for CEC controller
Use logical_address2 for CEC controller
use_all_bufs
bit.
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ADV8003 Hardware Manual

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