Antiglitch Filter Module - Analog Devices ADV8003 Hardware Manual

timestamp of 0b10 is assigned to receive buffer 0 to show that it contains the second received message. If the corresponding
interrupt mask bit is set,
was received.
6. Another message is received. This message is stored in receive buffer 2 (buffer 0 and buffer 1 are full). Time stamp 0b11 is
assigned to receive buffer 2 to show that it contains an unread message that was the third to be received. If the corresponding
interrupt mask bit is set,
was received. At this time all receive buffers are full and no more messages can be received until the processor reads at least one
message.
7. The host processor responds to the interrupts, or polls the timestamps and realizes that messages were received, and reads the
three time stamps. The buffer with the earliest time stamp should be read first. Therefore, receive buffer 1 is read first, followed
by receive buffer 0 and then receive buffer 2. Once the messages are read the processor clears cec_rx_ready_int[2:0]. The time
stamps for all three buffers are reset to 0b00.

7.4. ANTIGLITCH FILTER MODULE

This module is used to remove any glitches on the CEC bus in order to make the CEC input signal cleaner before it enters the CEC
module. The glitch filter is programmable through the
width that will be passed through by the module. Any pulses with narrower widths are rejected. There is a cec_glitch_filter_ctrl + 1
number of clock delays introduced by the antiglitch filter.
glitch_filter_ctrl[5:0], TX2 CEC Map, Address 0xF84F[5:0]
This signal is used to control the glitch filter. The CEC input signal is sampled by the input clock (XTAL clock). cec_glitch_filter_ctrl
specifies the minimum pulse width requirement in input clock cycles. Pulses of widths less than the minimum specified width are
considered glitches and will be removed.
Function
glitch_filter_ctrl[5:0]
000000
000001
000010
000111 
111111
Rev. B, August 2013
cec_rx_ready_int[2:0] goes high and an interrupt is generated to alert the host processor that a message
cec_rx_ready_int[2:0] goes high and an interrupt is generated to alert the host processor that a message
glitch_filter_ctrl[5:0]
Description
Disable glitch filter
Filter out pulses with width less than 1 clock cycle
Filter out pulses with width less than 2 clock cycles
...
Filter out pulses with width less than 7 clock cycles
...
Filter out pulses with width less than 63 clock cycles
register. The register value specifies the minimum pulse
301
ADV8003 Hardware Manual