Analog Devices ADV8003 Hardware Manual page 95

vid_ddr_yc_swap, IO Map, Address 0x1B4A[0]
This bit is used to swap the Luma (Y) and Chroma (C) data in DDR modes. By default, Y is expected on the rising edge of the clock.
Function
vid_ddr_yc_swap
0 
1
vid_ddr_edge_sel, IO Map, Address 0x1B4A[3]
This bit is used to select which edge the first sample of DDR data is latched on.
Function
vid_ddr_edge_sel
0 
1
Using the pixel clock as a reference, ADV8003 expects the Y sample on a rising edge and then a chroma sample on the falling edge. When
vid_ddr_yc_swap is set, ADV8003 expects a chroma sample on the rising edge and the Y sample on the falling edge.
can be used to swap the order of the chroma data. By default, ADV8003 expects a sequence of Cb, Cr, Cb, Cr... When
vid_swap_cb_cr_422 is set, ADV8003 expects a sequence of Cr, Cb, Cr, Cb....
vid_swap_cb_cr_422, IO Map, Address 0x1B49[7]
This bit is used to swap the order of the C data when decoding 4:2:2 data.
Function
vid_swap_cb_cr_422
0 
1
vid_ps444_r444_conv is used to convert from pseudo 444 video data to real 444. All processing occurs in the ADV8003 in 4:4:4 mode.
Therefore, if video input to the device is not in this format, this must be first converted to 4:4:4. Setting this bit to 1 converts video data to
4:4:4.
vid_ps444_r444_conv, IO Map, Address 0x1B49[6]
This bit is used to convert 4:2:2 data to pseudo 444 or to real 444.
Function
vid_ps444_r444_conv
0 
1
vid_hs_pol, vid_vs_pol, vid_de_pol
on the polarity of the upstream IC. If active low, these register can be left at their default. If these signals from the upstream IC are active
high, their polarity can be inverted.
vid_hs_pol, IO Map, Address 0x1B49[3]
This bit is used to set the polarity of the input HS timing signal.
Rev. B, August 2013
Description
Y on rising edge of clock
C on rising edge of clock
Description
Posedge data first
Negedge data first
Description
Cb/Cr decoding
Cr/Cb decoding
Description
Nothing done
Pseudo 444 to Real 444 conversion
and vid_fld_pol configure the polarity of the input video timing signals. These must be set depending
95
ADV8003 Hardware Manual
vid_swap_cb_cr_422