Video Encoder; Introduction; Input Configuration; Figure 104: Adv8003 Encoder Block Diagram - Analog Devices ADV8003 Hardware Manual

8. VIDEO ENCODER

8.1. INTRODUCTION

The ADV8003 encoder core consists of six high speed, Noise Shaped Video (NSV), 12-bit video DACs which provide support for
composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition (SD), enhanced definition (ED),
or high definition (HD) video formats.
Simultaneous SD and ED/HD input and output modes are supported. The ADV8003 encoder processor provides two independent signal
paths for SD and ED/HD, so different video processing (filtering, color conversion, and so on) can be individually and simultaneously
applied to each of the streams.
The input to the SD encoder block is always a 16/20/24-bit 4:2:2 YCbCr stream, and a 24/30/36-bit 4:4:4 YCbCr stream for ED/HD modes.
Although the encoder cannot take an RGB input stream in, it features a CSC matrix which enables the generation of RGB video signals at
the component output.
The oversampling at 216 MHz (SD and ED) and 297 MHz (HD) ensures that external output filtering is not required. The block diagram
for the ADV8003 encoder core is shown in
VBI DATA SERVICE
24-BIT
4:2:2 YCbCr
SD VIDEO
STREAM
36-BIT
4:4:4 YCbCr
EH/HD VIDEO
STREAM
Note: The video encoder variants of the ADV8003 are ADV8003KBCZ-8/7. The variants of ADV8003 with no encoder are
ADV8003KBCZ-8B/7B, ADV8003KBCZ-8C/7C and ADV8003KBCZ-7T.

8.2. INPUT CONFIGURATION

The ADV8003 encoder core is capable of supporting independent SD and ED/HD video outputs, and also both SD and ED/HD video in
simultaneous mode.
The data coming either from the VSP section or directly from the ADV8003 front-end input, is input to the SD encoder through two
8/10/12-bit SDR buses; the ED/HD encoder is accessed through three 8/10/12-bit SDR buses.
Rev. B, August 2013
Figure 104.
INSERTION
ADD
SYNC
YCbCr
SD TEST
ADD
PATTERN
BURST
GENERATOR
YCbCr
PROGRAMMABLE
HD TEST
SHARPNESS AND
PATTERN
ADAPTIVE FILTER
GENERATOR
VIDEO TIMING GENERATOR

Figure 104: ADV8003 Encoder Block Diagram

ENCODER PROCESSOR
SUBCARRIER FREQUENCY
I2C PORT
LOCK (SFL)
PROGRAMMABLE
LUMINANCE
FILTER
PROGRAMMABLE
SIN/COS DDS
CHROMINANCE
BLOCK
FILTER
YCbCr
HDTV FILTERS
TO
RGB MATRIX
CONTROL
307
16×
YCrCb
FILTER
TO
RGB
16×
FILTER
4×
FILTER
16x/4x OVERSAMPLING
DAC PLL
ADV8003 Hardware Manual
14-BIT
DAC 1
DAC 1
14-BIT
DAC 2
DAC 2
14-BIT
DAC 3
DAC 3
14-BIT
DAC 4
DAC 4
14-BIT
DAC 5
DAC 5
14-BIT
DAC 6
DAC 6