Analog Devices ADV8003 Hardware Manual page 145

de-interlacing, and so on), and then output this video from the PVSP. Many of the PVSP video processing functions are implemented in
the VOM. In game mode, the VOM will use data from the VIM instead of reading data from external memory.
The FFS is used to schedule and control the interaction between the VIM, external DDR2 memory, and the VOM. Field/frame buffer
scheduling, field polarity management, and FRC management are all implemented in the FFS.
The PVSP can be bypassed by setting pvsp_bypass.
pvsp_bypass, Primary VSP Map, Address 0xE829[7]
This bit is used to bypass the Primary VSP. If this bit is set to 1, the input video to the Primary VSP will be directly bypassed to the
output port.
Function
pvsp_bypass
0 
1
The VIM and VOM must be enabled if using the PVSP. This can be done by enabling the
This must be done regardless of the video conversions being performed.
pvsp_enable_vim, Primary VSP Map, Address 0xE828[1]
This bit is used to control the Video Input Module (VIM). If this bit is set to 1, the VIM is enabled to write packed input video data into
a defined external field/frame buffer. While the Primary VSP is running, if this bit is set to 0, the output video stream will be frozen.
Function
pvsp_enable_vim
0 
1
pvsp_enable_vom, Primary VSP Map, Address 0xE828[2]
This bit is used to control the Video Output Module (VOM). If this bit is set to 1, the VOM is enabled to read video data from external
memory, process it and then output it.
Function
pvsp_enable_vom
0 
1
Also, if using the PVSP, the FFS must be enabled using pvsp_enable_ffs. This informs the hardware of the various conversions that must
be performed. Field/frame buffers in external memory are managed by the FFS which decides which field/frame buffer should be used by
the VIM to store input video data. The FFS also decides which field/frame buffer should be read back by VOM to process. In the case of
interlaced video, the FFS informs the VOM if the input video is the even field or the odd field. The PVSP utilizes a frame repeat/drop
mechanism to implement FRC, which is also managed by the FFS.
pvsp_enable_ffs, Primary VSP Map, Address 0xE828[0]
This bit is used to control the Field Frame Scheduler (FFS). If this bit is set to 1, the FFS is enabled and the VIM and VOM are
scheduled by the FFS, which means the Primary VSP is in operating mode. If this bit is set to 0, the Primary VSP is in idle mode.
Rev. B, August 2013
Description
Not bypass Primary VSP
Bypass Primary VSP
Description
Disable VIM
Enable VIM
Description
Disable VOM
Enable VOM
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ADV8003 Hardware Manual
pvsp_enable_vim and pvsp_enable_vom bits.