Analog Devices ADV8003 Hardware Manual page 96

Function
vid_hs_pol
0 
1
vid_vs_pol, IO Map, Address 0x1B49[2]
This bit is used to set the polarity of the input VS timing signal.
Function
vid_vs_pol
0 
1
vid_de_pol, IO Map, Address 0x1B49[1]
This bit is used to set the polarity of the input DE enable signal.
Function
vid_de_pol
0 
1
vid_fld_pol, IO Map, Address 0x1B49[0]
This bit is used to set the polarity of the input Field (FLD) timing signal.
Function
vid_fld_pol
0 
1
vid_hs_vs_mode is used to select the method by which the input video will be synchronized. This may be required when the ADV8003 is
used in conjunction with an MPEG decoder. MPEG decoders use embedded timing codes rather than using external HS and VS signals.
Similarly, other ADI decoders/HDMI Rxs can output video using embedded timing codes. This register should be programmed
depending on the timing method of the upstream IC.
Refer to Section 2.2.11 for more information on AV-codes.
vid_hs_vs_mode, IO Map, Address 0x1B4B[7]
This bit is used to select the method of input timing.
Function
vid_hs_vs_mode
0
1 
vid_av_pos_sel, IO Map, Address 0x1B4B[3]
This bit is used to select if the HS generated is consistent with EIA 861 timing or dependant on the embedded timing codes.
Rev. B, August 2013
Description
Input HS polarity does not change
Input HS polarity gets inverted
Description
Input VS polarity does not change
Input VS polarity gets inverted
Description
Input DE polarity does not change
Input DE polarity gets inverted
Description
Input FLD polarity does not change
Input FLD polarity gets inverted
Description
Use embedded SAV/EAV codes
Use external HS/VS synchronization signals
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ADV8003 Hardware Manual