Table 27: Corresponding Bit For Each Cadence Type - Analog Devices ADV8003 Hardware Manual

Function
di_cadence_enable
0
1 
The PVSP supports the following cadence types:
• 2:2
• 2:2:2:4
• 3:2
• 2:3:3:2:2
• 2:3:3:2
• 3:2:3:2:2
• 3:3
• 4:4
• 5:5
•
6:4
• 8:7
Each of these cadence types can be disabled by setting the corresponding bit in
For conversion of 60 Hz interlaced and progressive input timing to 24 Hz progressive timing,
asserted. For all other cases,
pvsp_frc_change_phase_en, Primary VSP Map, Address 0xE84E[4]
This bit is used to lock the phase change for cadence detection.
Function
pvsp_frc_change_phase
_en
0
1 
di_fd_disabled_cadence[10:0], Primary VSP Map, Address 0xE8FA[7:0]; Address 0xE8FB[7:5]
This signal is used to disable corresponding cadence detection.
Function
di_fd_disabled_cadenc
e[10:0]
0x000 
Rev. B, August 2013
Description
Disable cadence detection
Enable cadence detection
pvsp_frc_change_phase_en
Description
Disable
Enable
Description
Default

Table 27: Corresponding Bit for Each Cadence Type

Bit
0xE8FB[5]
0xE8FB[6]
0xE8FB[7]
0xE8FA[0]
0xE8FA[1]
0xE8FA[2]
0xE8FA[3]
0xE8FA[4]
di_fd_disabled_cadence[10:0]
should be disabled when using 1 external DDR2 memory.
Disabled Cadence
2:2
2:2:2:4
3:2
2:3:3:2:2
2:3:3:2
3:2:3:2:2
3:3
4:4
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ADV8003 Hardware Manual
to 1.
pvsp_frc_change_phase_en should be