Subscribe to Our Youtube Channel
Related Manuals for Analog Devices ADV8003
Summary of Contents for Analog Devices ADV8003
- Page 1 ADV8003 Video Signal Processor with Motion Adaptive De- interlacing, Scaling, Bitmap OSD, Dual HDMI Tx and Video Encoder HARDWARE MANUAL Rev. B August 2013...
-
Page 2: Table Of Contents
ADV8003 Hardware Manual TABLE OF CONTENTS Understanding the ADV8003 Hardware Manual ......................10 Description of the Hardware Manual ............................10 Disclaimer ....................................... 10 Trademark and Service Mark Notice ............................10 Number Notations ..................................10 Register Access Conventions ................................ 10 Acronyms and Abbreviations ................................ 10 Field Function Description ................................ - Page 3 ADV8003 Hardware Manual 2.1.14. Mode 13 – OSD from HDMI RX ............................. 84 2.1.15. Mode 14 – Handling Triple Inputs ........................... 85 2.2. ADV8003 Top Level Overview ............................. 85 2.2.1. Video Muxing ..................................85 2.2.2. Digital Video Input ................................89 2.2.2.1.
- Page 4 ADV8003 Hardware Manual 3.2.1.7. Low Latency Mode ....................................154 3.2.1.8. Freezing Output Video ..................................155 3.2.1.9. Progressive Cadence Detection ................................155 3.2.2. PVSP Video Input Module..............................156 3.2.2.1. VIM Cropper ......................................156 3.2.2.2. Horizontal Down Scaler ..................................158 3.2.2.3. Scaler Interpolation Mode ................................... 158 3.2.2.4.
- Page 5 ADV8003 Hardware Manual 3.4.3. Gentle Reboot Protocol ..............................205 3.4.4. VOM Set Protocol ................................206 3.4.5. Free Access Protocol ................................206 3.5. Progressive to Interlaced Conversion .......................... 207 On Screen Display ..............................208 4.1. Introduction ..................................208 4.1.1. Features ....................................208 4.1.2.
- Page 6 ADV8003 Hardware Manual 6.1. General Controls ................................246 6.2. Reset Strategy .................................. 247 6.3. HDMI DVI Selection ..............................248 6.4. AV Mute ................................... 248 6.5. Source Product Description InfoFrame ........................249 6.6. Spare Packets ................................... 250 6.7. System Monitoring ................................. 252 6.7.1.
- Page 7 ADV8003 Hardware Manual 7.1. Main Controls ................................. 294 7.2. CEC Transmit Section..............................294 7.3. CEC Receive Section ..............................296 7.3.1. Logical Address Configuration ............................296 7.3.2. Receive Buffers ..................................297 7.3.3. CEC Message Reception Overview ..........................300 7.4. Antiglitch Filter Module ..............................301 7.5.
- Page 8 Encoder Component Placement ............................... 361 HDMI Transmitter Component Placement ............................. 361 Power Supply Design and Sequencing.............................. 361 Appendix B ..................................363 ADV8003 Evaluation Board Schematics ............................. 363 Appendix C ..................................393 ADV8003 Evaluation Board Layout ............................394 Appendix D ..................................402 Package Outline Drawing ................................
- Page 9 ADV8003 Hardware Manual Appendix F ..................................416 Pixel Input and Output Formats..............................416 List of Figures ..................................431 List of Tables ..................................435 List of Equations ................................437 Revision History ................................438 Rev. B, August 2013...
-
Page 10: Understanding The Adv8003 Hardware Manual
The content of this document is believed to be correct. If any errors are found within this document or, if clarification is needed, contact the authors at ATV_VSP_Apps@analog.com. TRADEMARK AND SERVICE MARK NOTICE The Analog Devices logo is a registered trademark of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. NUMBER NOTATIONS... - Page 11 Delay Locked Loop Direct Memory Access Digital Noise Reduction Data Preprocessor Direct Stream Digital Direct Stream Transfer Device Under Test (designate the ADV8003 unless stated otherwise) Digital Video Disc Digital Visual Interface End of Active Video Enhanced Definition Encoder Equalizer...
- Page 12 ADV8003 Hardware Manual Acronym/Abbreviation Description MPEG Moving Picture Expert Group Millisecond Most Significant Bit No Connect Noise Shaped Video On Screen Display One Time Programmable PtoI Progressive to Interlaced Pj’ HDCP Enhanced Link Verification Response. Refer to HDCP documentation. PVSP Primary VSP Ri’...
-
Page 13: Field Function Description
ADV8003 Hardware Manual FIELD FUNCTION DESCRIPTION The function of a field is described in a table preceded by the bit name, a short function description, the I C map, the register location within the I C map, and a detailed description of the field. Refer to Figure 1 for more details. -
Page 14: References
ADV8003 Hardware Manual REFERENCES HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4a, March 4, 2010 Digital Content Protection (DCP) LLC, High-bandwidth Digital Content Protection System, Revision 1.3, December 21, 2006 CEA, CEA-861-E, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision E, September 11, 2007 ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at the 4:2:2... -
Page 15: Introduction To The Adv8003
Dual video scalers allow the ADV8003 to support two different output resolutions on its outputs, for example, 1080p60 on HDMI TX1 and 720p on HDMI TX2 and the HD encoder. The primary VSP (PVSP) in the ADV8003 is capable of upscaling from 480i to 4k x 2k formats. -
Page 16: Digital Video Input
Digital Video Input Video data can be input into the ADV8003 in a number of ways. The flexible 60-bit TTL input port can be configured for dual video inputs (video TTL input and EXOSD TTL input), for a single video input (interleaved TTL data from an ADV7619) or for a single video input and an external alpha channel. -
Page 17: Flexible Digital Core
Flexible Digital Core The ADV8003 has a flexible digital core, allowing multiple options for the routing of video data. This allows the user to place the OSD in front of the video processing so the OSD will be overlaid on one or more outputs. Alternatively, video processing can be placed before the OSD ensuring all outputs are processed to the highest quality. -
Page 18: Bitmap On Screen Display
SPI flash memory via the SPI master (serial port 2). The ADV8003 uses DDR2 memory when rendering and blending the OSD. In order to lower the load of the DDR2 memory, there is a block in the ADV8003 OSD hardware called the OSD co-processor. -
Page 19: External Ddr2 Memory
Video Encoder The ADV8003 features a high speed digital to analog video encoder. Six high speed, NSV, 3.3 V, 12-bit video DACs provide support for worldwide composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition (SD), enhanced definition (ED), or high definition (HD) video formats. -
Page 20: Secondary Vsp
ADV8003 Hardware Manual • Noise reduction for random, mosquito, and block noise • Frame Rate Conversion • Color Upsampling Error (CUE) correction • Progressive to interlaced (PtoI) converter • Game mode supported • Album mode supported • Demo window 1.2.1.2. Secondary VSP •... -
Page 21: Adv8003 Functional Block Diagram
ADV8003 Hardware Manual 1.3. ADV8003 FUNCTIONAL BLOCK DIAGRAM CEC1 AUDIO DATA CAPTURE CONTROL CEC2 DDC1_SC L HDCP AND EDID DDC1_SD A UNCONTROLLER MASTER DDC2_SC L DDC2_SD A HPD_TX1 HPD_TX2 HDCP HDCP ENCRYPTION KEYS TX1_0+ 4:2:2 4:4:4 HDMI Tx TX1_0– VIDEO DATA... -
Page 22: Adv8003 Pinouts
ADV8003 Hardware Manual 1.4. ADV8003 PINOUTS OSD_ OSD_ OSD_ AUD_ AUD_ AUD_ ARC2_ IN[23]/ CLK/ MOSI1 SCK2 RESET XTALN PVDD2 CVDD1 RX_CN RX_0N RX_1N RX_2N CVDD1 RSET1 VREF EXT_ EXT_ IN[1] IN[2] IN[5] DIN[7] OSD_ OSD_ OSD_ IN[21]/ IN[22]/ AUD_... - Page 23 RSET1 Miscellaneous Resistor Current Setting for Encoder DACs: DAC1, DAC2, and DAC3. The RSET analog resistor should be placed as close as possible to the ADV8003. VREF Miscellaneous Optional External Voltage Reference Input for DACs or Voltage Reference Output. analog Place VREF voltage components as close as possible to the ADV8003.
- Page 24 Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control. Ground. INT0 Miscellaneous Interrupt Pin 0. When status bits change, this pin is triggered. digital Miscellaneous Power-Down. This pin controls the power state of the ADV8003. digital Ground. Ground. No connect Do not connect to this pin. No connect Do not connect to this pin.
- Page 25 Do not connect to this pin. RTERM HDMI Rx input This pin sets internal termination resistance. Use a 500 Ω resistor between this pin and GND. Place the RTERM resistor as close as possible to the ADV8003. AVDD2 Power Analog Power Supply (3.3 V).
- Page 26 Mnemonic Type Description RSET2 Miscellaneous Resistor Current Setting for Encoder DACs: DAC4, DAC5, and DAC6. Place the RSET analog resistor as close as possible to the ADV8003. PVDD3 Power PLL Supply (1.8 V). Ground. CEC1 HDMI Tx1 HDMI Tx1 Consumer Electronics Control (CEC).
- Page 27 ADV8003 Hardware Manual Mnemonic Type Description OSD_IN[0] OSD video input External OSD Video Pixel Input Port (OSD_IN[0]). DVDD Power Digital Power Supply (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. DVDD Power Digital Power Supply (1.8 V).
- Page 28 ADV8003 Hardware Manual Mnemonic Type Description Ground. Ground. Ground. Ground. HPD_TX1 HDMI Tx1 Hot Plug Assert Signal Input for HDMI Tx1. Ground. TX1_C+ HDMI Tx1 HDMI1 Clock True Output. TX1_C− HDMI Tx1 HDMI1 Clock Complementary Output. P[28] Digital video input Digital Video Input Bus[35:0].
- Page 29 ADV8003 Hardware Manual Mnemonic Type Description AVDD3 Power HDMI Analog Power Supply (1.8 V). No connect Do not connect to this pin. P[20] Digital video input Digital Video Input Bus[35:0]. P[21] Digital video input Digital Video Input Bus[35:0]. P[22] Digital video input Digital Video Input Bus[35:0].
- Page 30 ADV8003 Hardware Manual Mnemonic Type Description Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. HPD_TX2 HDMI Tx2 Hot Plug Assert Signal Input for HDMI Tx2. Ground. TX2_0+ HDMI Tx2 HDMI2 Channel 0 True Output. TX2_0− HDMI Tx2 HDMI2 Channel 0 Complementary Output.
- Page 31 Data Strobe for DDR Data Byte[31:24]. DDR_DQS[3] NC/GND No connect/GND For new ADV8003 designs, do not connect to this pin. For designs that must maintain consistency with the ADV8002, this pin can be grounded. DDR_A[8] DDR interface Address Line. Interface to external RAM address lines.
- Page 32 ADV8003 Hardware Manual Mnemonic Type Description AA20 DDR_DM[0] DDR interface Data Mask for Data Lines[7:0]. AA21 Ground. AA22 Ground. AA23 DDR_DQ[3] DDR interface Data Line. Interface to external RAM data lines. DDR_DQ[21] DDR interface Data Line. Interface to external RAM data lines.
- Page 33 Data Strobe for DDR Data Byte[7:0]. AC23 DDR_DQ[1] DDR interface Data Line. Interface to external RAM data lines. Sensitive node. Careful layout is important. The associated circuitry should be kept as close as possible to the ADV8003. Rev. B, August 2013...
-
Page 34: Figure 8. Adv8003Kbcz-8B And Adv8003Kbcz-7B Pin Configuration
ADV8003 Hardware Manual OSD_ OSD_ OSD_ AUD_ AUD_ AUD_ IN[23]/ CLK/ TEST4 MOSI1 SCK2 RESET XTALN PVDD2 CVDD1 RX_CN RX_0N RX_1N RX_2N CVDD1 EXT_ EXT_ IN[1] IN[2] IN[5] DIN[7] OSD_ OSD_ OSD_ AUD_ AUD_ ARC1_ IN[21]/ IN[22]/ MISO1 MOSI2 MISO2... - Page 35 Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM. Serial port control Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM. RESET Miscellaneous Reset Pin for the ADV8003. digital XTALN Miscellaneous Crystal Input.
- Page 36 Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control. Ground. INT0 Miscellaneous Interrupt Pin 0. When status bits change, this pin is triggered. digital Miscellaneous Power-Down. This pin controls the power state of the ADV8003. digital Ground. Ground. No connect Do not connect to this pin. No connect Do not connect to this pin.
- Page 37 Do not connect to this pin. RTERM HDMI Rx input This pin sets internal termination resistance. Use a 500 Ω resistor between this pin and GND. Place the RTERM resistor as close as possible to the ADV8003. AVDD2 Power Analog Power Supply (3.3 V).
- Page 38 ADV8003 Hardware Manual Mnemonic Type Description OSD_IN[8] OSD video input External OSD Video Pixel Input Port (OSD_IN[8]). Ground. Ground. Ground. DVDD Power Digital Power Supply (1.8 V). Ground. Ground. DVDD Power Digital Power Supply (1.8 V). Ground. Ground. Ground. Ground.
- Page 39 ADV8003 Hardware Manual Mnemonic Type Description Ground. Ground. Ground. DVDD Power Digital Power Supply (1.8 V). DDC1_SDA HDMI Tx1 HDCP Slave Serial Data for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to connect this pin to the HDMI Tx 5 V supply.
- Page 40 ADV8003 Hardware Manual Mnemonic Type Description P[28] Digital video input Digital Video Input Bus[35:0]. P[29] Digital video input Digital Video Input Bus[35:0]. P[30] Digital video input Digital Video Input Bus[35:0]. P[31] Digital video input Digital Video Input Bus[35:0]. Ground. Ground.
- Page 41 ADV8003 Hardware Manual Mnemonic Type Description Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. DVDD Power Digital Power Supply (1.8 V). No connect Do not connect to this pin. Ground. No connect Do not connect to this pin. No connect Do not connect to this pin.
- Page 42 ADV8003 Hardware Manual Mnemonic Type Description Ground. No connect Do not connect to this pin. No connect Do not connect to this pin. P[10] Digital video input Digital Video Input Bus[35:0]. P[11] Digital video input Digital Video Input Bus[35:0]. P[12] Digital video input Digital Video Input Bus[35:0].
- Page 43 DDR interface Data Strobe for DDR Data Byte[31:24]. NC/GND No connect/GND For new ADV8003 designs, do not connect to this pin. For designs that must maintain consistency with the ADV8002, this pin can be grounded. DDR_A[8] DDR interface Address Line. Interface to external RAM address lines.
- Page 44 Data Strobe for DDR Data Byte[7:0]. AC23 DDR_DQ[1] DDR interface Data Line. Interface to external RAM data lines. Sensitive node. Careful layout is important. The associated circuitry should be kept as close as possible to the ADV8003. Rev. B, August 2013...
-
Page 45: Figure 9. Adv8003Kbcz-8C And Adv8003Kbcz-7C Pin Configuration
ADV8003 Hardware Manual OSD_ OSD_ AUD_ AUD_ AUD_ ARC2_ IN[23]/ CLK/ OSD_ MOSI1 SCK2 RESET XTALN PVDD2 CVDD1 RX_CN RX_0N RX_1N RX_2N CVDD1 EXT_ EXT_ IN[1] IN[2] IN[5] DIN[7] OSD_ OSD_ OSD_ AUD_ AUD_ ARC1_ IN[21]/ IN[22]/ MISO1 MOSI2 MISO2... - Page 46 Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM. Serial port control Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM. RESET Miscellaneous Reset Pin for the ADV8003. digital XTALN Miscellaneous Crystal Input.
- Page 47 Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control. Ground. INT0 Miscellaneous Interrupt Pin 0. When status bits change, this pin is triggered. digital Miscellaneous Power-Down. This pin controls the power state of the ADV8003. digital Ground. Ground. No connect Do not connect to this pin. No connect Do not connect to this pin.
- Page 48 Do not connect to this pin. RTERM HDMI Rx input This pin sets internal termination resistance. Use a 500 Ω resistor between this pin and GND. Place the RTERM resistor as close as possible to the ADV8003. AVDD2 Power Analog Power Supply (3.3 V).
- Page 49 ADV8003 Hardware Manual Mnemonic Type Description OSD_IN[8] OSD video input External OSD Video Pixel Input Port (OSD_IN[8]). Ground. Ground. Ground. DVDD Power Digital Power Supply (1.8 V). Ground. Ground. DVDD Power Digital Power Supply (1.8 V). Ground. Ground. Ground. Ground.
- Page 50 ADV8003 Hardware Manual Mnemonic Type Description Ground. Ground. Ground. DVDD Power Digital Power Supply (1.8 V). DDC1_SDA HDMI Tx1 HDCP Slave Serial Data for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to connect this pin to the HDMI Tx 5 V supply.
- Page 51 ADV8003 Hardware Manual Mnemonic Type Description P[28] Digital video input Digital Video Input Bus[35:0]. P[29] Digital video input Digital Video Input Bus[35:0]. P[30] Digital video input Digital Video Input Bus[35:0]. P[31] Digital video input Digital Video Input Bus[35:0]. Ground. Ground.
- Page 52 ADV8003 Hardware Manual Mnemonic Type Description Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. DVDD Power Digital Power Supply (1.8 V). DDC2_SCL HDMI Tx2 HDCP Slave Serial Clock for HDMI Tx2. This pin is open drain; use a 2 kΩ resistor to connect this pin to the HDMI Tx 5 V supply.
- Page 53 ADV8003 Hardware Manual Mnemonic Type Description Ground. HPD_TX2 HDMI Tx2 Hot Plug Assert Signal Input for HDMI Tx2. Ground. TX2_0+ HDMI Tx2 HDMI2 Channel 0 True Output. TX2_0− HDMI Tx2 HDMI2 Channel 0 Complementary Output. P[10] Digital video input Digital Video Input Bus[35:0].
- Page 54 DDR interface Data Strobe for DDR Data Byte[31:24]. NC/GND No connect/GND For new ADV8003 designs, do not connect to this pin. For designs that must maintain consistency with the ADV8002, this pin can be grounded. DDR_A[8] DDR interface Address Line. Interface to external RAM address lines.
- Page 55 Data Strobe for DDR Data Byte[7:0]. DDR_DQS[0] AC23 DDR_DQ[1] DDR interface Data Line. Interface to external RAM data lines. Sensitive node. Careful layout is important. The associated circuitry should be kept as close as possible to the ADV8003. Rev. B, August 2013...
-
Page 56: Figure 10. Adv8003Kbcz-7T Pin Configuration
ADV8003 Hardware Manual OSD_ OSD_ OSD_ IN[23]/ CLK/ MOSI1 SCK2 RESET XTALN PVDD2 CVDD1 RX_CN RX_0N RX_1N RX_2N CVDD1 TEST4 TEST5 TEST6 TEST7 EXT_ EXT_ DIN[7] OSD_ OSD_ OSD_ IN[21]/ IN[22]/ TEST8 TEST9 TEST10 TEST11 MISO1 MOSI2 MISO2 ALSB XTALP... - Page 57 Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM. Serial port control Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM. RESET Miscellaneous digital Reset Pin for the ADV8003. XTALN Miscellaneous digital Crystal Input. PVDD2 Power PLL Digital Supply Voltage (1.8 V).
- Page 58 Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control. Ground. INT0 Miscellaneous digital Interrupt Pin 0. When status bits change, this pin is triggered. Miscellaneous digital Power-Down. This pin controls the power state of the ADV8003. Ground. Ground. No connect Do not connect to this pin. No connect Do not connect to this pin.
- Page 59 Do not connect to this pin. RTERM HDMI Rx input This pin sets internal termination resistance. Use a 500 Ω resistor between this pin and GND. Place the RTERM resistor as close as possible to the ADV8003. AVDD2 Power Analog Power Supply (3.3 V).
- Page 60 ADV8003 Hardware Manual OSD_IN[4] OSD video input External OSD Video Pixel Input Port (OSD_IN[4]). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. No connect Do not connect to this pin. No connect Do not connect to this pin.
- Page 61 ADV8003 Hardware Manual No connect Do not connect to this pin. Ground. No connect Do not connect to this pin. No connect Do not connect to this pin. P[32] Digital video input Digital Video Input Bus[35:0]. P[33] Digital video input Digital Video Input Bus[35:0].
- Page 62 ADV8003 Hardware Manual Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. No connect Do not connect to this pin. PVDD5 Power PLL Power Supply (1.8 V). This pin is a voltage regulator output. Connect a decoupling capacitor between this pin and ground.
- Page 63 ADV8003 Hardware Manual No connect Do not connect to this pin. P[14] Digital video input Digital Video Input Bus[35:0]. P[15] Digital video input Digital Video Input Bus[35:0]. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground.
- Page 64 Data Strobe for DDR Data Byte[31:24]. DDR_DQS[3] NC/GND No connect/GND For new ADV8003 designs, do not connect to this pin. For designs that must maintain consistency with the ADV8002, this pin can be grounded. DDR_A[8] DDR interface Address Line. Interface to external RAM address lines.
- Page 65 ADV8003 Hardware Manual AA20 DDR_DM[0] DDR interface Data Mask for Data Lines[7:0]. AA21 Ground. AA22 Ground. AA23 DDR_DQ[3] DDR interface Data Line. Interface to external RAM data lines. DDR_DQ[21] DDR interface Data Line. Interface to external RAM data lines. DDR_DQ[19] DDR interface Data Line.
- Page 66 ADV8003 Hardware Manual Sensitive node. Careful layout is important. The associated circuitry should be kept as close as possible to the ADV8003. Rev. B, August 2013...
-
Page 67: Protocol For Main I C Port
C slave address. All register maps within the ADV8003 can be accessed through this I C address through 16-bit addressing and 8-bit data registers. The ADV8003 acts as a standard slave device on the I C bus. It interprets the first byte as the I C address and the second byte and third bytes as the appropriate subaddress. -
Page 68: Configuring The Adv8003
1.6. CONFIGURING THE ADV8003 The ADV8003 requires a number of configuration settings for each mode of operation. To ensure the part is correctly configured, refer to either the recommended settings configuration script (supplied with the ADV8003 evaluation software) or the reference software driver. -
Page 69: Adv8003 Top Level Control
PVSP.) SVSP: This is the secondary scaler in the ADV8003 and is useful when providing an additional output resolution. The input to this block can only be progressive. This means an input format can only be connected to the SVSP if it is progressive or if it has been de-interlaced by the PVSP block. -
Page 70: Adv8003 Modes Of Operation
2.1. ADV8003 MODES OF OPERATION This section outlines the most practical modes in which the ADV8003 can be configured, as recommended by ADI. These modes describe the various ways to configure the VSP block, depending on the input formats as well as the outputs required. -
Page 71: Selecting A Mode
5 and mode 6 both use the PVSP and SVSP in parallel. However, as the SVSP can only accept progressive formats, input video to the ADV8003 must be progressive. If interlaced, only the PVSP can be used. Therefore, a note should be kept of the input formats if selecting these in parallel mode. -
Page 72: Figure 15: Adv8003 Mode 1 Configuration
& CSC & CSC Figure 15: ADV8003 Mode 1 Configuration Mode 1 places the PVSP after the input block. The output from this block is then sent to the SVSP or the PtoI converter. The OSD blend block can then be placed after the SVSP block. -
Page 73: Mode 2
& CSC & CSC Figure 16: ADV8003 Mode 2 Configuration Mode 2 places the PVSP after the input block. The output from this is sent to the OSD which is in turn sent to the SVSP or PtoI converter. This mode is very similar to mode 4, except that the OSD position has swapped with the PVSP. The primary reason is that, in this case, the OSD data is not overlaid on the incoming video data and then scaled, but rather scaled and then overlaid. -
Page 74: Mode 3
& CSC & CSC Figure 17: ADV8003 Mode 3 Configuration Both the PVSP and SVSP work in parallel in this mode. As the OSD is only on one data path, it will only be displayed at a single resolution. As shown in the example in Figure 17, the input to the SVSP must be a progressive format. -
Page 75: Mode 4
18, the input resolution is taken to be 480p. The OSD is downscaled, blended, and passed to the PVSP which scales to 1080p. The advantage of configuring the ADV8003 core in this way is that by including the PVSP on multiple data path, additional processing can be included on other outputs also. -
Page 76: Mode 5
& CSC & CSC Figure 19: ADV8003 Mode 5 Configuration Mode 5 places the OSD blend block before both the PVSP block and the SVSP block. Both the PVSP block and the SVSP work in parallel in this mode. As the OSD is before both scalers, the OSD will be available on all the outputs. As mentioned in Section 2.1.4, the input to the SVSP must be progressive, therefore, this mode can only be used when the input is progressive. -
Page 77: Mode 6
& CSC & CSC Figure 20: ADV8003 Mode 6 Configuration Mode 6 places the OSD blend block after the SVSP. Both the PVSP block and SVSP work in parallel in this mode. As the OSD is only on one data path, it will only be displayed at a single resolution. As shown in the example in... -
Page 78: Mode 7
& CSC & CSC Figure 21: ADV8003 Mode 7 Configuration Mode 7 is different to other modes in that OSD is not overlaid on video data on certain outputs but rather just output on its own. In certain cases where HDMI video from an upstream IC is copy protected, video data can be output on HDMI outputs but not analog outputs. -
Page 79: Mode 8
& CSC & CSC Figure 22: ADV8003 Mode 8 Configuration Mode 8 is similar to mode 7 in that OSD is not overlaid on the input video but rather output as the OSD video on its own. This may be... -
Page 80: Mode 9 - Bypass
& CSC & CSC Figure 23: ADV8003 Mode 9 Configuration Mode 9 is used in cases where no processing is required on the input video. This can be passed directly to the output. No access to external DDR2 memory is required in this case. -
Page 81: Mode 10 - Picture In Picture (Pip) (External Osd Less Than 720P)
& CSC & CSC Figure 24: ADV8003 Mode 10 Configuration Mode 10 is used to support the external input of either part of or the complete OSD from another device, for example, an MCU. With support for HS, VS, DE and CLK, the external OSD input can also be used to input video data. Using mode 10, the external OSD bus can be used to support picture in picture (PiP) with two video streams. -
Page 82: Mode 11 - Pip (External Osd Greater Than Or Equal To 720P)
CSC & ACE CSC & ACE 720p Video 720p Video (720p) (720p) Serial Serial Encoder Encoder from from Data Data Video Video Transceiver Transceiver Formatting Formatting & CSC & CSC Figure 25: ADV8003 Mode 11 Configuration Rev. B, August 2013... -
Page 83: Mode 12 - Dual Zone Osd
& CSC & CSC Figure 26: ADV8003 Mode 12 Configuration Mode 12 is used to support dual zone OSD output without disturbing either video stream. Using this mode, two inputs (for example, 480p from the video TTL input port and 720p from the Serial Video Rx) can be applied to the part, processed and connected to the OSD core. -
Page 84: Mode 13 - Osd From Hdmi Rx
ADV8003 Hardware Manual 2.1.14. Mode 13 – OSD from HDMI RX Mode 13 should be used if the ADV8003 is being used in conjunction with a legacy standalone OSD generator with an HDMI interface. Mode 13 Mode 13 DDR2 Memory... -
Page 85: Mode 14 - Handling Triple Inputs
2.2.1. Video Muxing There are several blocks which make up the ADV8003 VSP, as described in Section 2. The digital core of the ADV8003 offers flexible routing of video data, as shown in Figure Rev. B, August 2013... -
Page 86: Figure 29: Adv8003 Digital Core Muxing
RX Input Channel svsp_inp_sel[3:0] OSD Blend 2 sd_enc_inp_sel[3:0] External Secondary Input Channel RX Input Channel s_inp_chan_sel[1] ADV8003 Figure 29: ADV8003 Digital Core Muxing The following registers are used to configure the video routed through the ADV8003. Rev. B, August 2013... - Page 87 ADV8003 Hardware Manual tx1_inp_sel[3:0], IO Map, Address 0x1A03[7:4] This signal is used to select the video source for the HDMI Tx1. Function tx1_inp_sel[3:0] Description 0x00 From Main TTL Input 0x01 From Primary VSP 0x02 From PtoI Converter 0x03 From Internal OSD Blend 1...
- Page 88 ADV8003 Hardware Manual Function sd_enc_inp_sel[3:0] Description 0x00 From Main TTL Input 0x01 From Primary VSP 0x02 From PtoI Converter 0x03 From Internal OSD Blend 1 0x04 From Secondary VSP/PtoI Converter 0x05 From OSD TTL Input 0x06 From RX Input...
-
Page 89: Digital Video Input
0x04 From RX Input For example, when using the ADV8003 in mode 3 (described in Section 2.1.4), the following register settings are needed to configure the video data path: 1A 1A03 34; Output of OSD blend to HDMI Tx1, Output of Secondary VSP to HDMI Tx2 1A 1A04 30;... -
Page 90: Video Ttl Input
ADV8003 Hardware Manual Secondary Input Channel Video TTL Input Secondary Input Data AV-Code Up-dither Channel Video Output Rotate Detect EXOSD TTL Input Data External OSD Formatter Alpha Output Figure 31: EXOSD TTL Input Channel RX Input Channel >1080p 12-bit data... -
Page 91: Ttl Output
ADV8003 Hardware Manual 2.2.2.3. TTL Output The ADV8003 includes a TTL output port, The external OSD TTL input pins (OSD_IN[23:0]) and 12 of the TTL input pins (P35:24) can function as TTL output pins (refer to Table 98 Table 99). If all 36 TTL pins are used as outputs, this leaves only 24 pins for TTL inputs. - Page 92 ADV8003 Hardware Manual ttl_op_format[3:0], IO Map, Address 0x1A02[7:4] This signal is used to specify the TTL output format. Function ttl_op_format[3:0] Description 0000 8bit 422 0001 10bit 422 0010 12bit 422 0011 16bit 422 0100 20bit 422 0101 24bit 422 0110 24bit 444 0111 ...
-
Page 93: Serial Video Rx
2.2.2.5. Primary Input Channel The ADV8003 primary input channel incorporates an input formatter, CSC, updither block and ACE control. The input formatter provides a number of controls to configure what data the video TTL input channel is configured for. The video TTL input channel must be connected to either the video TTL input pins, the EXOSD TTL input pins or the high speed TTL input pins using p_inp_chan_sel[1:0]. -
Page 94: Figure 34: Ddr Mode, Luma And Chroma Swap
ADV8003 Hardware Manual Function vid_format_sel[4:0] Description 0x00 1 x 8-bit bus, SDR 4:2:2 0x01 1 x 10-bit bus, SDR 4:2:2 0x02 1 x 12-bit bus, SDR 4:2:2 0x03 2 x 8-bit buses, SDR 4:2:2 0x04 2 x 10-bit buses, SDR 4:2:2... - Page 95 Posedge data first Negedge data first Using the pixel clock as a reference, ADV8003 expects the Y sample on a rising edge and then a chroma sample on the falling edge. When vid_ddr_yc_swap is set, ADV8003 expects a chroma sample on the rising edge and the Y sample on the falling edge.
- Page 96 This may be required when the ADV8003 is used in conjunction with an MPEG decoder. MPEG decoders use embedded timing codes rather than using external HS and VS signals.
- Page 97 AV-codes are replicated. 0 AV-codes are not replicated. The updither feature in the ADV8003 can be used to randomize quantization errors, preventing large scale patterns such as color banding in images. Refer to Section 2.2.3 for more information on the updither block.
-
Page 98: Figure 35: Contrast Processing
ADV8003 Hardware Manual vid_ud_bypass_man, IO Map, Address 0x1B4A[1] This bit is used to bypass the up dither block. Function vid_ud_bypass_man Description 0 Disable bypass Enable bypass The primary input path features contrast, brightness and saturation controls. All contrast, brightness and saturation controls... -
Page 99: Figure 36: Brightness Processing
ADV8003 Hardware Manual brightness[7:0], IO Map, Address 0x1A2A[7:0] This register is used to adjust the brightness value for Y channel. The register uses s1.6 notation. Function brightness[7:0] Description 0x7F (+127) * 8 0x00 (No adjustment) * 8 0xFF (-1) * 8... -
Page 100: Secondary Input Channel
ACE controls for the primary input channel. 2.2.2.6. Secondary Input Channel The ADV8003 secondary input channel incorporates an input formatter, CSC and updither block. The input formatter provides a number of controls to configure what data the secondary input channel is configured for. The secondary input channel must be connected to either the video TTL input pins or the EXOSD TTL input pins using s_inp_chan_sel[1:0]. -
Page 101: Figure 38: Ddr Mode, Luma And Chroma Swap
ADV8003 Hardware Manual Function exosd_format_sel[4:0] Description 0x00 1 x 8 bit bus 4:2:2 0x01 1 x 10 bit bus 4:2:2 0x02 1 x 12 bit bus 4:2:2 0x03 2 x 8 bit buses 4:2:2 0x04 2 x 10 bit buses 4:2:2... - Page 102 Posedge data first Negedge data first Using the pixel clock as a reference, ADV8003 expects the Y sample on a rising edge and then a chroma sample on the falling edge. When exosd_ddr_yc_swap is set, ADV8003 expects a chroma sample on the rising edge and the Y sample on the falling edge.
- Page 103 This may be required when the ADV8003 is used in conjunction with an MPEG decoder. MPEG decoders use embedded timing codes rather than using external HS and VS signals.
- Page 104 AV-codes are replicated. 0 AV-codes are not replicated. The updither feature in the ADV8003 can be used to randomize quantization error preventing large scale patterns such as color banding in images. Refer to Section 2.2.3 for more information on the updither block.
-
Page 105: Rx Input Channel
2.2.2.7. RX Input Channel The ADV8003 RX input channel incorporates an input formatter, CSC and updither block. The updither feature in the ADV8003 can be used to randomize quantization error preventing large scale patterns such as color banding in images. Refer to Section 2.2.3 for more information on the updither... -
Page 106: Updither Configuration
The updither block can be used in a situation where the video input to the ADV8003 is in 8-bit form and must be converted to 10-bit or 12-bit for output. -
Page 107: Figure 40: Configuring Input Port Clock
ADV8003 Hardware Manual OSD_IN[35] Secondary OSD_IN[0] OSD_VS Inputs OSD_HS OSD_DE Set by exosd_in_id P[35] P[35] Main P[0] P[0] Inputs Set by vid_in_id Rx2+ Rx2+ Rx2- Rx2- Serial Rx1+ Rx1+ Rx1- Rx1- Video Rx0+ Rx0+ Rx0- Rx0- RxC+ RxC+ RxC- RxC-... - Page 108 ADV8003 Hardware Manual video_in_id[7:0], IO Map, Address 0x1A00[7:0] This register is used to set the output clock frequencies from the input video formatting block used by both the HDMI RX inputs and Video TTL input ports. Function video_in_id[7:0] Description 0x01...
- Page 109 CEA861 VIC 24 (288p50 2x) The ADV8003 can output a large number of video formats including many common graphics resolutions. To enable the PVSP and SVSP cores to output these frequencies, the output timing clocks must first be programmed. The output clocks for both the PVSP and SVSP are...
-
Page 110: Figure 41: Pvsp/Svsp Output Clock Configure
ADV8003 Hardware Manual Primary Primary Primary VSP Primary VSP dpll clock dpll clock Secondary Secondary Secondary VSP Secondary VSP dpll clock dpll clock Figure 41: PVSP/SVSP Output Clock Configure For the PVSP and SVSP, the correct clocks must be configured manually. This can be done using the DPLL period registers, which allows the user to program the sampling rate for the appropriate output format by I C. -
Page 111: Pvsp Output Timing
Depending on the sampling frequency required, the following registers need to be programmed with this DPLL clock period. Note: To enable the DPLL to configure the correct clocks for the ADV8003, register 0x0039 must be set to 0x0A. This register must always be configured before the following registers are set. -
Page 112: Frame Tracking
2.2.4.3. Frame Tracking The ADV8003 employs frame tracking on its scaler outputs. There will always be some error in the input frame rate versus the ideal frame rate. This could cause frame drops or repeats at the output. Frame tracking allows the output timing to track the input timing in such a way that eliminates frame drops and repeats while also remaining immune to discontinuities in the input. -
Page 113: Ddr2 Interface
Adjust for frequency difference between input and output vertical sync 2.2.5. DDR2 Interface The ADV8003 uses DDR2 memory to enable the de-interlacer, scaler and OSD features. The DDR2 interface on ADV8003 is designed to meet the JESD79-2F standard. 2.2.5.1. DDR2 Configuration The controls described in this section are used to configure the ADV8003 DDR2 memory interface. - Page 114 ADV8003 Hardware Manual ADV8003 is configured for dual 512 Mbit memories with a 64-bit word size and bursts of 4. sdram_size[3:0], IO Map, Address 0x1A5B[7:4] This signal is used to specify the SDRAM size. All values other than those specified here are reserved.
-
Page 115: Ddr2 Bandwidth And Memory Selection
2.2.5.2. DDR2 Bandwidth and Memory Selection The DDR2 interface on ADV8003 can be configured to work with one or two (default) DDR2 memories. Using a single DDR2 memory limits the amount of functionality. Different capabilities are possible with different memory sizes. An outline of expected limitations are... -
Page 116: Table 11: Indication Of Adv8003 Capabilities With Two Ddr2 Memories
ADV8003 Hardware Manual Table 11: Indication of ADV8003 Capabilities with Two DDR2 Memories Features Motion Random Noise Dual Output (ADV8003-1 Adaptive De- Reduction only) interlacing SD input Supported Supported Supported Total area of all OSD Supported regions (on screen at same... -
Page 117: Single Ddr2 Memory Configuration
2.2.5.4. DDR2 Loopback Test The ADV8003 features a DDR2 loopback test block to allow testing of the ADV8003 DDR2 interface. When the loopback test block is enabled, it controls the commands sent to the DDR2 controller of the ADV8003 and generates pseudo random data and addresses using a defined protocol. -
Page 118: I 2 C Auto Increment
ADV8003 Hardware Manual 1A 1AA8 B4 ; Recommended Write 1A 1AFE 08 ; Recommended Write 1A 1A0B 10 ; Recommended Write 1A E649 40 ; Recommended Write A single memory DD2 loopback test is initialized and started via the following writes: 1A 1A5B 22 ;... -
Page 119: Spi Loop Through
ADV8003 Hardware Manual ADV8003. By default, this is set to 1 which means that a read from a particular address in the ADV8003 increments the read pointer to the next register map address. read_auto_inc_en, IO Map, Address 0x1AFC[0] This register is used to auto increment I2C addresses in the device for consecutive reads. -
Page 120: Ancillary Data Extraction
ADV8003 Hardware Manual vbi_src (1 = SPI, 0 = ANC) sclk External spi_rx_dv Sync mosi Slave Master ccap_even_data ccap_out ccap_even_dv ccap_ext_out 1’b1 ccap_odd_data Ancillary Ancillary Data Data To Encoder ccap_odd_dv Extractor Delay cgms_wss_out_sd cgms_wss_data hdmi_rx_clk spi_rx_dv[7:0] muxed_vid_in cgms_wss_dv cgms_wss_out_hd vid_rx_clk... -
Page 121: Spi Data Extraction
If there is not an input video data bus which can provide the ancillary data, it may be serialized and sent to the part via a SPI master. The ADV8003 contains a dedicated SPI slave for receiving VBI data. The SPI interface receives serialized ancillary data bytes. All of the ancillary data packets must be encoded, including the preamble. -
Page 122: Resets
Resets This section documents the register bits used for resetting various sections of the ADV8003. These resets can be used by the system controller to reset individual sections of the device without having to reset the whole part. If the whole device needs to be reset, this can be implemented by setting the global reset, main_reset. - Page 123 ADV8003 Hardware Manual Function p2i_reset Description 0 Default Reset ddr2_intf_reset, IO Map, Address 0x1AFD[4] (Self-Clearing) This bit is used to reset the external DDR memory interface core. Function ddr2_intf_reset Description 0 Default Reset spi_reset, IO Map, Address 0x1AFD[3] (Self-Clearing) This bit is used to reset the SPI hardware, both master and slave.
- Page 124 ADV8003 Hardware Manual Function rx_reset Description 0 Default Reset enc_reset, IO Map, Address 0x1AFE[6] (Self-Clearing) This bit is used to reset the HD and SD encoders. Function enc_reset Description 0 Default Reset tx2_reset, IO Map, Address 0x1AFE[5] (Self-Clearing) This bit is used to reset the HDMI TX2.
-
Page 125: Image Processing Colorimetry Breakdown
2.2.11. AV-Codes Embedded end of active video (EAV) and start of active video (SAV) timing codes are supported on the TTL inputs of the ADV8003. AV- code information is embedded into the pixel data and is transmitted using a standard 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. - Page 126 ADV8003 Hardware Manual • 1080p50 • VGA (640x480) • SVGA (800x600) • XGA (1027x768 • WXGA (1280x768) • SXGA (1280x1024) • WXGA (1360x768) • UXGA (1600x1200) • WXGA(1366x768 • WUXGA (1900x1200) A number of CEA formats are not supported automatically for AV-codes •...
- Page 127 ADV8003 Hardware Manual Function hs_beg_pos[9:0] Description 0xXX Assert hs when hcount reaches 0xXX hs_end_pos[9:0], IO Map, Address 0x1A7D[5:0]; Address 0x1A7E[7:4] This signal is used to select the HS ending position, counting from the EAV, if CEA 861 timing generation is enabled and manual values selected.
- Page 128 ADV8003 Hardware Manual Function de_v_beg_e_pos[6:0] Description 0xXX assert de when lcount reaches 0xXX on even fields de_v_beg_o_pos[6:0], IO Map, Address 0x1B8C[0]; Address 0x1B8D[7:2] This signal is used to specify the DE vertical beginning position for odd fields, if CEA 861 timing generation is enable and manual values selected.
- Page 129 ADV8003 Hardware Manual Function vs_h_beg_e_pos[10:0] Description 0xXX assert vs when hcount reaches 0xXX on even fields vs_v_beg_pos[5:0], IO Map, Address 0x1B94[3:0]; Address 0x1B95[7:6] This signal is used to specify the vertical beginning position of VS, if CEA 861 timing generation is enable and manual values selected.
-
Page 130: Color Space Conversion
2.2.12. Color Space Conversion Although all processing in the ADV8003 is performed in the YCbCr color space, the part is capable of receiving video in the RGB, YUV and YCbCr color spaces. The ADV8003 provides any-to-any CSC on each of the inputs and on both of the outputs (five color space converters in all). - Page 131 ADV8003 Hardware Manual vid_csc_enable, IO Map, Address 0x1B30[7] This bit is used to control the Primary Input Channel CSC. Function vid_csc_enable Description 0 CSC disable CSC enable vid_csc_mode[1:0], IO Map, Address 0x1B30[6:5] This signal is used to specify the CSC mode for the Primary Input Channel CSC. The CSC mode sets the fixed point position of the CSC coefficients, including a4, b4, c4 and offsets.
- Page 132 ADV8003 Hardware Manual The video inputs In_A, In_B and In_C are connected by default to R, G and B. Refer to Table 14 for more information. The default routing can be changed by adjusting the value of vid_swap_bus_ctrl[2:0]. Table 14: Default Primary Input Channel CSC Signal Routing...
-
Page 133: Secondary Input Channel Csc
ADV8003 Hardware Manual Color Space Conversion RGB (full) SDTV YCbCr 0x1 0x0833 0x0000 0x0099 0x1F99 0x1E56 0x0800 0x1F13 0x014B 0x00EA 0x0000 0x0826 0x1F78 (limited) to HDTV YCbCr (limited) SDTV YCbCr 0x1 0x091B 0x0000 0x0000 0x1F6E 0x0000 0x0950 0x0000 0x1F6B 0x0000 0x0000 0x091B 0x1F6E... -
Page 134: Figure 48: Secondary Input Channel Csc
ADV8003 Hardware Manual Function exosd_csc_enable Description 0 CSC disable CSC enable exosd_csc_mode[1:0], IO Map, Address 0x1B50[6:5] This signal is used to specify the CSC mode for the Secondary Input Channel CSC. The CSC mode sets the fixed point position of the CSC coefficients, including a4, b4, c4 and offsets. - Page 135 ADV8003 Hardware Manual Table 16: Default Secondary Input Channel CSC Signal Routing Input Channel Default RGB Routing Default YCbCr Routing In_A In_B In_C The A1 to A3, B1 to B3, and C1 to C3 coefficients are used to scale the primary inputs. A4, B4 and C4 are added as offsets. Floating point coefficients must be converted into 120-bit fixed decimal format then converted into binary format using twos complement for negative values and can only be programmed in the range [-1….+1] or [-4096….+4095].
-
Page 136: Rx Input Channel Csc
ADV8003 Hardware Manual Color Space Conversion HDTV YCbCr (limited) SDTV YCbCr 0x1 0x091B 0x0000 0x0000 0x1F6E 0x0000 0x0950 0x0000 0x1F6B 0x0000 0x0000 0x091B 0x1F6E (limited) to SDTV YCbCr (full) SDTV YCbCr 0x1 0x0AF8 0x0800 0x0000 0x1A84 0x1A6A 0x0800 0x1D50 0x0423 0x1FFC 0x0800 0x0DDE 0x1913... -
Page 137: Figure 49: Rx Input Channel Csc
ADV8003 Hardware Manual Function rx_csc_enable Description 0 CSC disable CSC enable rx_csc_mode[1:0], IO Map, Address 0x1B70[6:5] This signal is used to specify the CSC mode for the RX input channel CSC. The CSC mode sets the fixed point position of the CSC coefficients, including a4, b4, c4 and offsets. - Page 138 ADV8003 Hardware Manual Table 18: Default RX Input Channel CSC Signal Routing Input Channel Default RGB Routing Default YCbCr Routing In_A In_B In_C The A1 to A3, B1 to B3, and C1 to C3 coefficients are used to scale the primary inputs. A4, B4 and C4 are added as offsets. Floating point coefficients must be converted into 120-bit fixed decimal format then converted into binary format using twos complement for negative values and can only be programmed in the range [-1….+1] or [-4096….+4095].
-
Page 139: Hdmi Transmitter Cscs
ADV8003 Hardware Manual Color Space Conversion HDTV YCbCr (limited) SDTV YCbCr 0x1 0x091B 0x0000 0x0000 0x1F6E 0x0000 0x0950 0x0000 0x1F6B 0x0000 0x0000 0x091B 0x1F6E (limited) to SDTV YCbCr (full) SDTV YCbCr 0x1 0x0AF8 0x0800 0x0000 0x1A84 0x1A6A 0x0800 0x1D50 0x0423 0x1FFC 0x0800 0x0DDE 0x1913... -
Page 140: Figure 50: Hdmi Tx Csc
ADV8003 Hardware Manual Function csc_en Description 0 CSC disabled CSC enabled csc_scaling_factor[1:0], TX2 Main Map, Address 0xF418[6:5] This signal is used to specify the CSC scaling factor. The CSC scaling factor sets the fixed point position of the CSC coefficients, including a4, b4, c4 and offsets. - Page 141 ADV8003 Hardware Manual Table 20: Default HDMI TX Channel CSC Signal Routing Input Channel Default RGB Routing Default YCbCr Routing In_A In_B In_C The A1 to A3, B1 to B3, and C1 to C3 coefficients are used to scale the primary inputs. A4, B4 and C4 are added as offsets. Floating point coefficients must be converted into 120-bit fixed decimal format then converted into binary format using twos complement for negative values and can only be programmed in the range [-1….+1] or [-4096….+4095].
-
Page 142: Adv8003 Silicon Revision
0x0000 0x0000 0x0000 0x0000 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000 (Output = Input) 2.2.13. ADV8003 Silicon Revision The ADV8003 silicon revision can be determined using rb_chip_id[15:0]. rb_chip_id[15:0], IO Map, Address 0x1AD0[7:0]; Address 0x1AD1[7:0]; This signal is used to readback the unique silicon revision ID. Function... -
Page 143: System Configuration
ADV8003 Hardware Manual 2.2.14. System Configuration When configuring a system featuring an HDMI Rx and ADV8003, the following sequences for HDMI Tx and encoder are recommended. For HDMI Tx: Configure the HDMI Rx (ADV7850). Wait until the ADV8003 Serial Video Rx achieves lock. -
Page 144: Video Signal Processing
This section details the registers used to control the Video Signal Processing (VSP) hardware. The three constituent sections of the ADV8003 video processor are the PVSP, SVSP, and the PtoI converter. These hardware blocks are completely independent of each other and can be placed in various configurations within the ADV8003. - Page 145 ADV8003 Hardware Manual de-interlacing, and so on), and then output this video from the PVSP. Many of the PVSP video processing functions are implemented in the VOM. In game mode, the VOM will use data from the VIM instead of reading data from external memory.
-
Page 146: Autoconfiguration
ADV8003 Hardware Manual Function pvsp_enable_ffs Description 0 Disable FFS/FRC Enable FFS/FRC 3.2.1.1. Autoconfiguration Each block inside VIM and VOM can be automatically configured to reduce the configuration complexity. Two registers, pvsp_autocfg_input_vid[7:0] pvsp_autocfg_output_vid[7:0] should be set to make the autoconfiguration work. -
Page 147: Table 23: Pvsp Supported Output Video Timing And Vid
ADV8003 Hardware Manual Video Timing 480p240 56 or 57 480i240 58 or 59 SVGA WXGA VESA timing SXGA WXGA-2 UXGA WXGA-3 WUXGA Note: The PVSP does not support the CEA-861 VIC 60 and CEA-861 VIC 61 formats. pvsp_autocfg_output_vid[7:0], Primary VSP Map, Address 0xE882[7:0] This register is used to set the output timing VIC. -
Page 148: Customized Input/Output Video Format Configuration
ADV8003 Hardware Manual Video Timing 4kx2k 25 Hz 4kx2k 24 Hz 4kx2k 24 Hz SMPTE SVGA WXGA VESA SXGA timing WXGA-2 UXGA WXGA-3 WUXGA Note: The PVSP does not support the following formats; • 1280x720p @ 23.97/24 Hz (CEA VIC 60) •... -
Page 149: Field/Frame Buffer Number
ADV8003 Hardware Manual Function pvsp_vin_v[10:0] Description 0x000 Default 0xXXX Vertical resolution of input video Similarly, if the output timing is not in the PVSP output format table, customized output format needs to be set manually. The detailed configuration instructions are given in the PVSP VOM output port description. - Page 150 ADV8003 Hardware Manual pvsp_fieldbuffer2_addr[31:0] = 70800 (7372800 in hex) Note: The default value of the field/frame buffer is set for a 1080p input. If the maximum supported video is 1080p, there is no need to change the setting of the field/frame buffer. It is recommended to leave the setting of the buffer number and the buffer size unchanged.
-
Page 151: Frame Latency
ADV8003 Hardware Manual Function pvsp_fieldbuffer4_addr Description [31:0] 0x02495A00 Default 0xXXXXXXXX Start address of field/frame buffer 4 pvsp_fieldbuffer5_addr[31:0], Primary VSP Map, Address 0xE814[7:0]; Address 0xE815[7:0]; Address 0xE816[7:0]; Address 0xE817[7:0] This signal is used to set the start address of field/frame buffer 5. The software should arrange memory space properly, avoiding conflict between different buffers. - Page 152 ADV8003 Hardware Manual Output Frame Rate 50 Hz 59.94/60 Hz 23.97/24 Hz 25/30 Hz Input Frame rate Timing 576p/720p/1080 480p/720p/1080p 720p/1080p 720p/1080p /4kx2k /4kx2k 23.97/24/25/30 720/1080p 0.1~0.8 0.1~0.8 0.1~1.3 0.1~1.3 x.x means x.x times the input video field/frame A~B means frame latency is not a fixed value, it varies between A and B If cadence detection is disabled, this value should be 0.3~1.4 with setting...
-
Page 153: Game Mode
Album mode The functions listed as autodisabled do not need to be manually disabled in game mode – ADV8003 will automatically disable them when game mode is enabled. Functions which are not listed as autodisabled must be manually disabled before game mode is enabled. -
Page 154: Low Latency Mode
3.2.1.7. Low Latency Mode Game mode has a very small frame latency but some processing functions cannot be supported in this mode. ADV8003 provides another mode, low latency mode, which can support frame rate change, scaling, crop and album mode. -
Page 155: Freezing Output Video
ADV8003 when the input video is 60 Hz and the output video is 24 Hz. An example of progressive cadence detection would involve the ADV8003 detecting a pull-down ratio of 3:2 for 60 Hz video and reconverting this to its original film content at 24 Hz. This would allow the video to be output at 24 Hz and, therefore, be displayed at the highest image quality possible. -
Page 156: Pvsp Video Input Module
ADV8003 Hardware Manual 3.2.2. PVSP Video Input Module Video Input Module (VIM) Video Input Module (VIM) Input Input Horizontal Horizontal Video Video Cropper Cropper Down Scaler Down Scaler Pixel Pixel Packer Packer Write to Write to DDR2 DDR2 Figure 53: PVSP Video Input Module 3.2.2.1. - Page 157 ADV8003 Hardware Manual pvsp_vim_crop_h_start[10:0], Primary VSP Map, Address 0xE832[2:0]; Address 0xE833[7:0] This signal is used to set the horizontal start position of the VIM cropper. Function pvsp_vim_crop_h_start Description [10:0] 0x000 Default 0xXXX Horizontal start position of VIM cropper input pvsp_vim_crop_v_start[10:0], Primary VSP Map, Address 0xE834[2:0];...
-
Page 158: Horizontal Down Scaler
ADV8003 Hardware Manual 3.2.2.2. Horizontal Down Scaler Although the VOM has both horizontal and vertical scalers, there is also a horizontal down scaler in the VIM. The purpose of the VIM down scaler is to save external memory bandwidth by doing horizontal downscaling before writing video data into the external memory to save memory bandwidth. -
Page 159: Scaler Controls
This register can be set at any time, but it may take some time (not more than 300 ms) to become valid. This delay is related to the ADV8003 taking control of the memory format change to avoid the display of garbage information. -
Page 160: Pvsp Video Output Module
ADV8003 Hardware Manual pvsp_ex_mem_data_format[1:0], Primary VSP Map, Address 0xE829[4:3] This signal is used to set the data format in external memory. Function pvsp_ex_mem_data_for Description mat[1:0] 00 YCbCr-12b-10b-10b YCbCr-8b-8b-8b YCbCr-4:2:4-12b YCbCr-4:2:2-8b Table 26 indicates the number of bytes required when storing a particular type of video data. -
Page 161: Pixel Unpacker
• Scaler: scales video to target resolution • Output port: generates output timing and output video Register update protection is provided in the ADV8003. Refer to Section 3.4 for more details regarding how to update the various VSP registers. pvsp_lock_vom, Primary VSP Map, Address 0xE828[3] This bit is used to lock the Video Output Module (VOM). -
Page 162: Figure 56: Vom Crop Dimensions
ADV8003 Hardware Manual • pvsp_di_crop_v_start[10:0] • pvsp_di_crop_width[10:0] • pvsp_di_crop_height[10:0] To enable cropper in VOM, pvsp_di_crop_enable should be asserted. pvsp_di_crop_enable, Primary VSP Map, Address 0xE883[4] This bit is used to enable the VOM crop. Function pvsp_di_crop_enable Description 0 Disable VOM crop... -
Page 163: Motion Detection
+ pvsp_di_crop_height[10:0]) <= VERTICAL RESOLUTION OUTPUT BY VIM 3.2.3.3. Motion Detection The ADV8003 de-interlacer is used to convert interlaced video to progressive video. The PVSP has an extremely high quality de-interlacer algorithm which achieves excellent quality interlaced to progressive conversion. The algorithm uses motion adaptive de-interlacing technology, which includes motion detection, cadence detection, low angle detection and interpolation. -
Page 164: Low Angle De-Interlacing
Enable ULAI 3.2.3.5. Cadence Detection The ADV8003 cadence detection can handle multiple different types of cadences, typically introduced when content originated as film format but was converted into interlaced format for broadcast. Examples of such conversion can be seen in Figure 52. -
Page 165: Table 27: Corresponding Bit For Each Cadence Type
ADV8003 Hardware Manual Function di_cadence_enable Description Disable cadence detection 1 Enable cadence detection The PVSP supports the following cadence types: • • 2:2:2:4 • • 2:3:3:2:2 • 2:3:3:2 • 3:2:3:2:2 • • • • • Each of these cadence types can be disabled by setting the corresponding bit in di_fd_disabled_cadence[10:0] to 1. -
Page 166: Cue Correction
3.2.3.7. Random Noise Reduction There are several noise reduction algorithms in the ADV8003 that help with the reduction of common sources of video noise. The random noise reduction (RNR) block reduces the random noise which may be introduced in analog broadcasting or capturing. It employs a temporal recursive algorithm to stabilize the static regions while just processing the luma channel. -
Page 167: Mosquito Noise Reduction
3.2.3.8. Mosquito Noise Reduction The second type of noise reduction algorithm implemented in the ADV8003 is the mosquito noise reduction (MNR). The MNR block selectively removes ringing artifacts introduced into highly compressed (MPEG) video data. For the best results, this block should be enabled when the input video is not being scaled, due to the fact that it is easier to identify and remove compressed artifacts at lower resolutions. -
Page 168: Block Noise Reduction
ADV8003 Hardware Manual Function di_mnr_level[1:0] Description 10 Middle High To get better image performance, register di_mnr_th_min[3:0] can be used to set the MNR level. di_mnr_th_min[3:0], Primary VSP Map 2, Address 0xE917[7:4] This signal is used to set the strength of the mosquito noise reduction (MNR). The larger the value, the stronger the MNR noise reduction. - Page 169 ADV8003 Hardware Manual Function di_bnr_edge_offset[7:0] Description 0x32 Recommended setting for low level BNR 0x64 Recommended value for mid level BNR 0x96 Recommended value for high level BNR di_bnr_disable_local_detect, Primary VSP Map 2, Address 0xE987[3] This bit is used to configure the BNR processing.
-
Page 170: Sharpness Enhancement
The ADV8003 scaler employs contour-based interpolation techniques to provide sharp edges and crisp details on high resolution content. The embedded compression noise reduction will eliminate mosquito noise and block artifacts. The contour-based interpolation scaler is capable of upscaling input video formats from 480i to 4k x 2k formats (these include 4k x 2k 30 Hz/4k x 2k 25 Hz/4k x 2k 24 Hz and 4k x 2k 24 Hz SMPTE). - Page 171 ADV8003 Hardware Manual Function pvsp_srscal_interp_mo Description de[1:0] 00 Automatic scaler algorithm selection Contour-based interpolation scaler (2nd gen scaling algorithm with 4k x 2k support) Frequency-adaptive scaler (1st gen scaling algorithm) Bilinear scaler pvsp_srscal_8bit_en, Primary VSP Map, Address 0xE890[3] This bit is used to set the scaler into 8-bit mode. This bit should be set when output 4K x 2K timing.
-
Page 172: Panorama Mode
ADV8003 Hardware Manual Image before Image before Scaler in Scaler in Scaled Image Scaled Image Scaler Scaler VSP3D_SCAL_OUT_HEIGHT PVSP_SCAL_OUT_HEIGHT VSP3D_DI_CROP_HEIGHT PVSP_DI_CROP_HEIGHT PVSP_DI_CROP_WIDTH PVSP_SCAL_OUT_WIDTH Figure 57: VOM Scaler Dimensions 3.2.3.12. Panorama Mode If the scaled video has a different aspect ratio to the original and the horizontal scaling factor is larger than the vertical, the panorama function can be enabled using m_scaler_panorama_en. -
Page 173: Output Port
Table 29 for the register settings for the common CEA video formats that are supported by the ADV8003. The output setting can be automatically configured using the setting of pvsp_autocfg_output_vid[7:0]. If the output configuration needs to be set manually, pvsp_man_dp_timing_enable... - Page 174 ADV8003 Hardware Manual Function pvsp_man_dp_timing_ Description enable 0 Disable manually setting output timing Enable manually setting output timing pvsp_dp_decount[12:0], Primary VSP Map, Address 0xE856[4:0]; Address 0xE857[7:0] This signal is used to set the DE duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.
- Page 175 ADV8003 Hardware Manual Function pvsp_dp_activeline[11: Description 0x000 Default 0xXXX Active lines of output timing pvsp_dp_vfrontporch[9:0], Primary VSP Map, Address 0xE860[1:0]; Address 0xE861[7:0] This signal is used to set the vertical front porch duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.
-
Page 176: Figure 59: Vom Output Dimensions
ADV8003 Hardware Manual Function pvsp_dp_hpolarity Description 0 High Table 29: Output Port Configuration Settings for Example Output Resolutions decount hfrontporch HSync hbackporch activeline Vfrontporch VSync vbackporch hpol vpol Output Timing 0xE8 0xE8 0xE8 0xE8 0xE8 0xE8 0xE8 0xE8 0xE8... -
Page 177: Demo Function
Not output default color Output default color 3.2.3.14. Demo Function ADV8003 supports automatically splitting the display window to demo several processing functions of ADV8003. pvsp_demo_window_enable can be used to enable the demo function. pvsp_demo_window_enable, Primary VSP Map, Address 0xE87E[7] Enables demo window. - Page 178 ADV8003 Hardware Manual The following registers can be used to enable each corresponding demo function. pvsp_demo_window_rnr_enable, Primary VSP Map, Address 0xE87E[4] This bit is used to enable the RNR in the demo window. Function pvsp_demo_window_rn Description r_enable 0 Disable RNR in demo window...
-
Page 179: Progressive To Interlaced Converter
ADV8003 Hardware Manual Function pvsp_demo_window_c Description ue_enable 0 Disable CUE in demo window Enable CUE in demo window pvsp_demo_window_intra_field_enable, Primary VSP Map, Address 0xE87F[4] This bit is used to enable the intra field interpolation in the demo window. Function... -
Page 180: Automatic Contrast Enhancement
Write to Write to DDR2 DDR2 DDR2 DDR2 Figure 60: ADV8003 SVSP Figure 60 shows the structure of the SVSP. The SVSP comprises of four sections; the VIM, the VOM, a controller which is the FFS, and a PtoI converter. - Page 181 ADV8003 Hardware Manual The SVSP can be used to offer the option of a second output resolution to the user. The structure of the SVSP is similar to the PVSP but it is much simpler in design and does not contain all the processing elements of the PVSP. The structure of the SVSP comprises FFS, VIM, and VOM blocks.
-
Page 182: Autoconfiguration
ADV8003 Hardware Manual svsp_enable_vom, Secondary VSP Map, Address 0xE610[5] This bit is used to control the Video Output Module (VOM). If this bit is set to 1, the VOM is enabled to read video data from external memory, process it and then output it. -
Page 183: Table 32: Svsp Supported Output Video Timing And Vid
ADV8003 Hardware Manual Video Timing 1920x1080p24 1920x1080p25 1920x1080p30 720p100 576p100 42 or 43 720p120 480p120 48 or 49 576p200 52 or 53 480p240 56 or 57 SVGA WXGA VESA timing SXGA WXGA-2 UXGA WXGA-3 WUXGA Note: The SVSP does not support the following formats: •... -
Page 184: Customized Input/Output Video Format Configuration
ADV8003 Hardware Manual Video Timing 1280x720p50 1920x1080i50 720x576i50 21 or 22 or 25 or 26 720x288p50 23 or 24 or 27 or 28 1920x1080p50 1920x1080p24 1920x1080p25 1920x1080p30 720p100 576p100 42 or 43 720p120 480p120 48 or 49 576p200 52 or 53... -
Page 185: Frame Buffer Number
ADV8003 Hardware Manual Function svsp_vin_h[10:0] Description 0x000 Default 0xXXX Horizontal resolution of input video svsp_vin_v[10:0], Secondary VSP Map, Address 0xE618[7:0]; Address 0xE619[7:5] This signal is used to set the vertical resolution of the input video. This register's value will be used while svsp_man_input_res is 1 or svsp_autocfg_input_vid is 1. - Page 186 ADV8003 Hardware Manual svsp_fieldbuffer0_addr[31:0], Secondary VSP Map, Address 0xE600[7:0]; Address 0xE601[7:0]; Address 0xE602[7:0]; Address 0xE603[7:0] This signal is used to set the start address of frame buffer 0. The software should arrange memory space properly, avoiding conflict between different buffers.
-
Page 187: Frame Latency
3.3.1.5. Frame Latency Depending on the format being input to the ADV8003 and the output required from the SVSP, different resolutions will have different frame latencies. This is due to the increased processing required on scaling different types of video data. This has a certain impact in that the audio will have to be delayed by the same amount. - Page 188 ADV8003 Hardware Manual When crop or album mode is enabled, frame latency will be different from that listed in Table 33. In this case, the user can use the following controls to measure frame latency: svsp_rb_frame_latency[2:0] svsp_rb_hsync_latency[11:0] are read only registers. Their values are real-time frame and HSync latency between input and output video.
-
Page 189: Freezing Output Video
ADV8003 Hardware Manual svsp_rb_min_latency[14:0], Secondary VSP Map, Address 0xE6F7[7:0]; Address 0xE6F8[7:1] (Read Only) This signal is used to read back the minimum frame/HSync latency. The upper three bits are VSync latency, the lower twelve bits are HSync latency. Function svsp_rb_min_latency[1... -
Page 190: Figure 62: Vim Crop Dimensions
ADV8003 Hardware Manual This bit is used to enables the VIM crop. Function svsp_vim_crop_enable Description 0 Disable Enable Figure 62 shows the correlation between the cropped image and the input video resolution. Input Video Input Video SVSP_VIM_CROP_V_START Cropped Image... -
Page 191: Scaler
ADV8003 Hardware Manual svsp_vim_crop_height[10:0], Secondary VSP Map, Address 0xE620[7:0]; Address 0xE621[7:5] This signal is used to set the input height of the VIM cropper. Function svsp_vim_crop_height[ Description 10:0] 0x000 Default 0xXXX Height of VIM cropper input Note: The following limitations apply to the values that can be programmed in these registers: •... -
Page 192: Scaler Interpolation Mode
ADV8003 Hardware Manual Image before Image before Scaler in Scaler in Scaled Image Scaled Image Scaler Scaler VSP2D_VIM_SCAL_OUT_HEIGHT SVSP_VIM_SCAL_OUT_HEIGHT VSP2D_VIM_CROP_HEIGHT SVSP_VIM_CROP_HEIGHT SVSP_VIM_CROP_WIDTH SVSP_VIM_SCAL_OUT_WIDTH Figure 63: VIM Scaler Dimensions 3.3.2.3. Scaler Interpolation Mode This section describes the method for scaling the input video data. The purpose of the scaler is to allow different input formats to be displayed on a screen with a fixed resolution. -
Page 193: Panorama Mode
ADV8003 Hardware Manual Function svsp_vim_scal_anti_alia Description s_v_en Disable 1 Enable svsp_vim_scal_type[1:0], svsp_vim_scal_anti_alias_h_en svsp_vim_scal_anti_alias_v_en can be manually set. These settings take effect only when svsp_man_scaler_para_enable is set to 1, otherwise they can be automatically configured by the SVSP using svsp_autocfg_input_vid[7:0] and svsp_autocfg_output_vid[7:0]. -
Page 194: Pixel Packer
ADV8003 Hardware Manual svsp_vim_scal_pano_pos[10:0], Secondary VSP Map, Address 0xE651[7:0]; Address 0xE652[7:5] This signal is used to define the width of the output video frame which is not stretched when panorama mode is enabled but rather scaled properly. The maximum value of this register is set by: svsp_vim_crop_width * (svsp_vim_scal_out_height/svsp_vim_crop_height) - svsp_vim_scal_out_width/2. -
Page 195: Pixel Unpacker
VOM cropper: reads cropped images from external memory • Output port: generates output timing and output video Register update protection is provided in the ADV8003. Refer to Section 3.4 for more details regarding the update of the various VSP registers. -
Page 196: Figure 65: Vom Crop Dimensions
ADV8003 Hardware Manual svsp_vom_crop_enable, Secondary VSP Map, Address 0xE662[1] This bit is used to enable the VOM crop. Function svsp_vom_crop_enable Description 0 Disable Enable Video Image in External Memory Video Image in External Memory SVSP_VOM_CROP_V_START Cropped Image Cropped Image... -
Page 197: Output Port
ADV8003 Hardware Manual Function svsp_vom_crop_width[ Description 10:0] 0x000 Default 0xXXX Width of VOM cropper input svsp_vom_crop_height[10:0], Secondary VSP Map, Address 0xE62C[7:0]; Address 0xE62D[7:5] This signal is used to set the height of the VOM cropper. Function svsp_vom_crop_height[ Description 10:0] 0x000 ... - Page 198 ADV8003 Hardware Manual Function svsp_dp_hfrontporch[9: Description 0x000 Default 0xXXX Horizontal front porch of output timing svsp_dp_hsynctime[9:0], Secondary VSP Map, Address 0xE636[7:0]; Address 0xE637[7:6] This signal is used to set the HSync duration of output timing. This register's value will be used while svsp_autocfg_output_vid is 0.
-
Page 199: Table 34: Output Port Configuration Settings For Example Output Formats
ADV8003 Hardware Manual Function svsp_dp_vsynctime[9:0] Description 0x000 Default 0xXXX VSync width of output timing svsp_dp_vbackporch[9:0], Secondary VSP Map, Address 0xE640[7:0]; Address 0xE641[7:6] This signal is used to set the vertical back porch duration of output timing. This register's value will be used while svsp_autocfg_output_vid is 0. -
Page 200: Figure 66: Vom Output Dimensions
ADV8003 Hardware Manual svsp_dp_margin_color[23:0] register in the YUV color space. This feature can be enabled using svsp_dp_output_blank. Output video from Primary VSP Output video from Primary VSP SVSP_DP_VIDEO_V_START Output video from Output video from VSP2D_DP_VIDEO_H_START SVSP_DP_VIDEO_H_START VOM Output VOM Output... -
Page 201: Ddr Bypass Mode
ADV8003 Hardware Manual Function svsp_dp_output_blank Description 0 Not output default color Output default color 3.3.3.4. DDR Bypass Mode In the case where the SVSP is being used to upscale or downscale between 1080p and 720p, external DDR2 memory is not required. -
Page 202: Vsp Register Access Protocols
ADV8003 Hardware Manual The input video to the PtoI block is defined using svsp_p2i_vid[7:0]. For more details on the values which must be programmed into this register, refer to Table svsp_p2i_vid[7:0], Secondary VSP Map, Address 0xE64A[7:0] 'This register is used to set the VIC of the PtoI in Secondary VSP. -
Page 203: Reboot Protocol
ADV8003 Hardware Manual Figure 67: Bootup Protocol Flowchart Figure 67 shows the process for the bootup protocol for the PVSP. This is exactly the same for the SVSP with the appropriate registers replaced. 3.4.2. Reboot Protocol The reboot protocol is used to reset the PVSP and configure it again using different settings, especially different input timing or output timing. -
Page 204: Figure 68: Reboot Protocol Flowchart
ADV8003 Hardware Manual Figure 68: Reboot Protocol Flowchart Figure 68 shows the process for the reboot protocol for the PVSP. This is exactly the same for the SVSP with the appropriate registers replaced. Rev. B, August 2013... -
Page 205: Gentle Reboot Protocol
ADV8003 Hardware Manual 3.4.3. Gentle Reboot Protocol The gentle reboot is used to reboot the PVSP with different configuration settings but does not interrupt the output timing. The output video is frozen during this protocol. All registers except output video timing registers can be accessed. -
Page 206: Vom Set Protocol
ADV8003 Hardware Manual 3.4.4. VOM Set Protocol The VOM set protocol is used to configure the VOM. The registers in the VOM can be accessed without affecting the output video timing. Figure 70: VOM Set Protocol Flowchart Figure 70 shows the process for the VOM set protocol for the PVSP. This is exactly the same for the SVSP with the appropriate registers replaced. -
Page 207: Progressive To Interlaced Conversion
ADV8003 Hardware Manual 3.5. PROGRESSIVE TO INTERLACED CONVERSION ADV8003 has two progressive to interlaced converters (P2I). The primary P2I converter is an independent block to which the PVSP, OSD and inputs can be connected. The primary P2I converter can convert from any progressive format to its interlaced equivalent. The input to the primary P2I converter is selected by p2i_inp_sel[3:0]. -
Page 208: On Screen Display
4.1. INTRODUCTION The On Screen Display (OSD) core in the ADV8003 allows the user to overlay a bitmap-based OSD onto one of the input video streams. The OSD blend is capable of being performed at data rates up to 3 GHz (ADV8003KBCZ-8x derivatives). The OSD can be designed using the ADI Blimp software tool. -
Page 209: Typical Osd Component Sizes
Section 4.1.2, the OSD core in the ADV8003 is controlled mainly via a SPI slave interface and loads images and OSD data into the part via a SPI master interface. Consequently, a number of the configuration registers for the OSD core are SPI registers and the code required to control these registers is automatically generated by the Blimp OSD software tool –... -
Page 210: Osd Blending
4.2.3. OSD Blending The OSD core in the ADV8003 has two video inputs and two video outputs and is capable of blending at data rates of up to 3 GHz (ADV8003KBCZ-8x derivatives). The two video inputs allow two different video streams to be connected to the OSD core, for example, video TTL input channel and SVSP output. -
Page 211: External Alpha Blending
External Alpha Blending The ADV8003 features an external alpha blend input which is shared with the input pixel port. The external alpha blend can only be used in conjunction with the EXOSD TTL input. This allows the option to specify an external alpha blend value for the EXOSD TTL input channel. -
Page 212: Osd Core Region Definition
ADV8003 Hardware Manual Function osd_reset Description 0 Default Resets OSD core 4.2.5.1. OSD Core Region Definition 75. The regions are derived from the OSD components defined in the Blimp A region defines an area on the plane, as shown in Figure OSD software and, therefore, contain the different elements of the OSD, for example, the text, images, icons, and so on. -
Page 213: Osd Color Space
4.2.5.2. OSD Color Space Bitmap images as well as external OSDs are passed to the OSD core in 8-bit RGB format. However, all video processing in the ADV8003 takes place in YCbCr. The OSD core features a CSC to enable conversion of the OSD data from RGB to YCbCr. The OSD core CSC can convert into either full of limited range YCbCr. - Page 214 ADV8003 Hardware Manual Function timer1_enable Description 0 Disables Enables Once the timer is enabled, disabling this bit will stop the counting, and it will be resumed when enabling back this bit. Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (i.e. bit[1] controls timer2, bit[2] controls timer3, etc.);...
- Page 215 ADV8003 Hardware Manual timer1_irq_en, SPI Device Address 0x0B (TIMER), Address 0x07[0] Timer 1 interrupt enable. Function timer1_irq_en Description 0 Disable Enable Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (that is, bit[1] controls timer2, bit[2] controls timer3, and so on);...
- Page 216 ADV8003 Hardware Manual timer6_interval[31:0], SPI Device Address 0x0B (TIMER), Address 0x1E[7:0]; Address 0x1F[7:0]; Address 0x20[7:0]; Address 0x21[7:0] Timer 6 interval, unit is ms. timer7_interval[31:0], SPI Device Address 0x0B (TIMER), Address 0x22[7:0]; Address 0x23[7:0]; Address 0x24[7:0]; Address 0x25[7:0] Timer 7 interval, unit is ms.
-
Page 217: Osd Scaler
OSD Master/Slave SPI Interface The ADV8003 OSD requires an external DDR2 memory and some configuration done to the OSD SPI registers in order to work. OSD data can be written to the DDR2 memory on startup by the ADV8003. In addition, to dynamically configure the OSD, configuration registers need to be controlled. -
Page 218: Overview
The ADV8003 SPI master interface (serial port 2) can pull in resource data to DDR2 memory from an external SPI flash memory, as shown in Figure • The system MCU (SPI master) can write OSD data into DDR2 memory using the ADV8003 SPI slave interface (serial port 1), as shown in Figure Config... -
Page 219: Figure 78: Mcu As Spi Master Sending Osd Data Through Adv8003 Spi Slave Interface
DDR2 Memory Controller(CPU) Figure 78: MCU as SPI Master Sending OSD Data Through ADV8003 SPI Slave Interface Additionally, the system MCU (SPI master) can program the external flash by looping SPI commands through the SPI slave (serial port 1) and the SPI master (serial port 2) interfaces connected in a chain. In this mode, the OSD core just passes through MOSI, SS and SCLK signals from the MCU to the flash. -
Page 220: Figure 79: Spi Loopback Enabled So Mcu Can Program Spi Flash
ADV8003 Hardware Manual Config Register OSD_CORE Master Slave Slave FLASH System DDR2 Memory Controller(CPU) Figure 79: SPI Loopback Enabled so MCU Can Program SPI Flash By default, the SPI ports are set in manual mode for the SPI which means the SPI pins are tristated (input). To make the SPI ports operational, the following register bits must be configured to automatic mode. - Page 221 ADV8003 Hardware Manual spi1_sclk_oe_man_en, IO Map, Address 0x1ACE[4] This bit is used to control the output enable manual override for spi1_sclk. Function spi1_sclk_oe_man_en Description Auto 1 Manual override spi2_cs_oe_man_en, IO Map, Address 0x1ACE[3] This bit is used to control the output enable manual override for spi2_cs.
- Page 222 ADV8003 Hardware Manual Function spi1_cs_oe_man Description 0 Input Output spi1_miso_oe_man, IO Map, Address 0x1ACD[6] This bit is used to control the output enable for spi1 'master in slave out'. Function spi1_miso_oe_man Description 0 Input Output spi1_mosi_oe_man, IO Map, Address 0x1ACD[5] This bit is used to control the output enable for spi1 'master out slave in'.
-
Page 223: Spi Slave Interface
4.2.8.2. SPI Slave Interface The ADV8003 SPI slave interface (serial port 1) is used by the MCU to send the OSD data to the DDR2 and to configure the OSD registers. Note that the SPI functions provided within the ADI libraries will automatically take care of any SPI transfer between the MCU and ADV8003. - Page 224 If SCK1 is slower than 6 MHz, no delay mode can be set. The ADV8003 features an analog antiglitch used to reject glitches on SCK1 (SPI slave). There are three modes of operation of this filter: bypass, 2 ns glitch rejection, and 5ns glitch rejection. The 2 ns glitch rejection mode should be used for clock frequencies between 10MHz and 40 MHz.
-
Page 225: Spi Master Interface
4.2.8.3. SPI Master Interface The ADV8003 SPI master interface (serial port 2) is used by the ADV8003 to read the OSD binary file (output by Blimp OSD) from an external SPI flash memory, and to copy it to the DDR2 memory. Note that the library of functions provided by ADI will take care of this process;... -
Page 226: Osd Initialization
0 Negedge used Posedge used 4.2.9. OSD Initialization To configure ADV8003 to use the OSD, the following I C writes are required: 0x1A14=0x0C: SPI mode select 0x1ACE=0x00: SPI bus enable 0x1ACC=0x10: Configure OSD HW int Further SPI writes are required but these are controlled through the OSD. -
Page 227: Serial Video Receiver
5.1. + 5 V DETECT The Serial Video Rx on the ADV8003 can monitor the level on the +5 V power signal pin. This +5 V signal can be used to reset the Rx section if requested. If +5 V detection is not being used, this pin should be connected to a +5 V supply. The controls for +5 V detection can be found in the following I C registers. -
Page 228: Tmds Clock Activity Detection
5.2. TMDS CLOCK ACTIVITY DETECTION The ADV8003 Serial Video Rx provides circuitry to monitor TMDS clock activity and also the type of data on the Rx input lines. System software can poll these registers and configure the ADV8003 as required. -
Page 229: Clock And Data Termination Control
AVMUTE set 5.5. DEEP COLOR MODE SUPPORT The ADV8003 supports HDMI streams with 24-bits per sample and deep color modes. The addition of a video FIFO (refer to Section 5.6 for more details) allows for the robust support of these modes. -
Page 230: Video Fifo
1X rate for non deep color modes (8-bits per channel), and 1.25X, 1.5X, or 2X for deep color modes (30, 36 and 48 bits respectively). Data unpacking and data rate reduction must be performed on the incoming data to provide the ADV8003 digital core with the correct data rate and data bit width. -
Page 231: Figure 83: Hdmi Video Fifo
ADV8003 Hardware Manual T M D S T M D S C l o c k P L L D P L L D i v i d e r T M D S C h 0 T M D S... -
Page 232: Pixel Repetition
In HDMI mode, video formats with TMDS rates below 25 Mpixels/s require pixel repetition in order to be transmitted over the serial video link. When the ADV8003 receives this type of video format, it discards repeated pixel data automatically, based on the pixel repetition field available in the AVI InfoFrame. -
Page 233: Sync Signal Polarity Readbacks
ADV8003 Hardware Manual Function hdmi_pixel_repetition[ Description 3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 - 1111 Reserved derep_n_override, HDMI RX Map, Address 0xE241[4] This bit allows the user to override the pixel repetition factor. DEREP_N is then used instead of hdmi_pixel_repetition[3:0] to discard video pixel data from the incoming HDMI stream. -
Page 234: Figure 84: Horizontal Timing Parameters
ADV8003 Hardware Manual Data Enable HSYNC Total number of pixels per line HSync width in pixel unit Active number of pixels per line HSync back porch width in pixel unit HSync front porch width in pixel unit Figure 84: Horizontal Timing Parameters dvi_vsync_polarity, HDMI RX Map, Address 0xE205[4] (Read Only) This bit is a readback to indicate the polarity of the VSync encoded in the input stream. -
Page 235: Infoframe Registers
ADV8003 Hardware Manual 5.9. INFOFRAME REGISTERS In HDMI, the auxiliary data is carried across the digital link using a series of packets. The ADV8003 Serial Video Rx can automatically detect and store the following HDMI packets: • InfoFrames • Audio content protection •... -
Page 236: Avi Infoframe Registers
ADV8003 Hardware Manual 5.9.3. AVI InfoFrame Registers Table 38 provides a list of readback registers for the AVI InfoFrame data. Refer to the EIA/CEA-861 specifications for a detailed explanation of the AVI InfoFrame fields. Table 38: AVI InfoFrame Registers InfoFrame... -
Page 237: Spd Infoframe Registers
ADV8003 Hardware Manual 5.9.4. SPD InfoFrame Registers Table 39 provides a list of readback registers available for the SPD InfoFrame. Refer to the EIA/CEA-861 specifications for a detailed explanation of the SPD InfoFrame fields. Table 39: SPD InfoFrame Registers InfoFrame... -
Page 238: Mpeg Source Infoframe Registers
ADV8003 Hardware Manual 5.9.5. MPEG Source InfoFrame Registers Table 40 provides a list of readback registers available for the MPEG InfoFrame. Refer to the EIA/CEA-861 specifications for a detailed explanation of the MPEG InfoFrame fields. Table 40: MPEG InfoFrame Registers... -
Page 239: Packet Registers
ADV8003 Hardware Manual InfoFrame Register Name Byte Name Map Address 0xE35F vs_inf_pb_0_12 Data Byte 11 0xE360 vs_inf_pb_0_13 Data Byte 12 0xE361 vs_inf_pb_0_14 Data Byte 13 0xE362 vs_inf_pb_0_15 Data Byte 14 0xE363 vs_inf_pb_0_16 Data Byte 15 0xE364 vs_inf_pb_0_17 Data Byte 16... -
Page 240: Table 43: Isrc2 Packet Registers
ADV8003 Hardware Manual InfoFrame Register Name Packet Byte No. Map Address 0x9B isrc1_pb_0_16 PB15 0x9C isrc1_pb_0_17 PB16 0x9D isrc1_pb_0_18 PB17 0x9E isrc1_pb_0_19 PB18 0x9F isrc1_pb_0_20 PB19 0xA0 isrc1_pb_0_21 PB20 0xA1 isrc1_pb_0_22 PB21 0xA2 isrc1_pb_0_23 PB22 0xA3 isrc1_pb_0_24 PB23 0xA4 isrc1_pb_0_25... -
Page 241: Gamut Metadata Packets
ADV8003 Hardware Manual InfoFrame Register Name Packet Byte No. Map Address 0x E3B8 isrc2_pb_0_17 PB16 0x E3B9 isrc2_pb_0_18 PB17 0x E3BA isrc2_pb_0_19 PB18 0x E3BB isrc2_pb_0_20 PB19 0x E3BC isrc2_pb_0_21 PB20 0x E3BD isrc2_pb_0_22 PB21 0x E3BE isrc2_pb_0_23 PB22 0x E3BF... -
Page 242: Customizing Packet/Infoframe Storage Registers
The packet type value of each set of packet and InfoFrame registers in the Serial Video Rx InfoFrame Map is programmable. This allows the user to configure the ADV8003 to store the payload data of any packet and InfoFrames sent by the transmitter connected on the Serial Video Rx port. - Page 243 ADV8003 Hardware Manual Function aud_packet_id[7:0] Description 0xxxxxxx Packet type value of packet stored in InfoFrame Map, Address 0x1C to 0x29 1xxxxxxx Packet type value of InfoFrame stored in InfoFrame Map, Address 0x1C to 0x29 ms_packet_id[7:0], HDMI RX Infoframe Map, Address 0xE3E9[7:0] This signal is a readback of the MPEG Source InfoFrame ID.
-
Page 244: Hdmi Section Reset Strategy
5.12. HDMI SECTION RESET STRATEGY The following reset strategy is implemented for the HDMI section: • Global chip reset – This means the ADV8003 Serial Video Rx core can be reset using the rx_reset or main_reset. A global chip reset is triggered by asserting the RESET pin to a low level. The HDMI section is reset when a global reset is triggered. -
Page 245: Hdmi Transmitter
ADV8003 Hardware Manual 6. HDMI TRANSMITTER The HDMI transmitters on the ADV8003 are capable of outputting video data at up to 3 GHz (ADV8003KBCZ-8/8B/8C only) and support 3D video output, ARC, CEC and audio output. Note that the 3 GHz transmitter variants of ADV8003 are the following: •... -
Page 246: General Controls
A typical implementation for a sink is to tie the transmitter 5 V power signal to HPD through a series resistor. In this case, the ADV8003 will detect a high level on HPD_TX1 (HPD_TX2 for HDMI Tx 2) regardless of whether or not the downstream sink is powered on and ready to receive a TMDS stream. -
Page 247: Reset Strategy
ADV8003 Hardware Manual Function hpd_override[1:0] Description 00 HPD from HPD pin and CDC HPD HPD from CDC HPD HPD from HPD pin HPD set to 1 rx_sense_state, TX2 Main Map, Address 0xF442[5] (Read Only) This bit is used to readback the state of the Rx sense. -
Page 248: Hdmi Dvi Selection
HDMI DVI SELECTION The HDMI Tx core supports the transmission of both HDMI and DVI streams. The type of stream the ADV8003 transmits is set via hdmi_mode_sel. In DVI transmission mode, no packets will be sent and all registers relating to packets and InfoFrames will be disregarded. -
Page 249: Source Product Description Infoframe
ADV8003 Hardware Manual Function set_avmute Description 0 Set set_avmute to 0 Set set_avmute to 1 clear_avmute, TX2 Main Map, Address 0xF44B[7] This bit is used to control the clear_avmute signal. Function clear_avmute Description 0 Set clear_avmute to 0 Set clear_avmute to 1 6.5. -
Page 250: Spare Packets
Data Byte 27 6.6. SPARE PACKETS The user may configure the ADV8003 to send any type of packets or InfoFrames via the spare packets controls and associated configuration registers. The ADV8003 features two such spare packets that can be enabled via the... -
Page 251: Table 51: Spare Packet 1 Configuration Register
ADV8003 Hardware Manual Packet Map Access Type Register Name Default Value Byte Name Address 0xF2C8 spare1_pb5[7:0] 0b00000000 Data Byte 5 0xF2C9 spare1_pb6[7:0] 0b00000000 Data Byte 6 0xF2CA spare1_pb7[7:0] 0b00000000 Data Byte 7 0xF2CB spare1_pb8[7:0] 0b00000000 Data Byte 8 0xF2CC spare1_pb9[7:0]... -
Page 252: System Monitoring
Data Byte 27 6.7. SYSTEM MONITORING 6.7.1. General Status and Interrupts The ADV8003 utilizes both interrupts and status bits to indicate the status of internal operations and errors in the Tx core. These interrupt and status are listed in Table Table... -
Page 253: Edid/Hdcp Controller Error Codes
6.10.1. Input Format The HDMI Tx core of the ADV8003 receives video data from the ADV8003 digital core via a 36-bit wide bus and four synchronization signals: the pixel clock, the data enable, the horizontal and vertical synchronization signals. The HDMI Tx core always receives the video data in a 4:4:4 and SDR format from the VSP core. -
Page 254: Video Mode Detection
The detected VIC is sent in the AVI InfoFrames unless pixel repetition is applied to the video stream transmitted by the ADV8003. When pixel repetition is applied to the video data, the VIC sent in the AVI InfoFrame may be different as the VIC is automatically determined by the ADV8003. -
Page 255: Pixel Repetition
Pixel repetition is used in HDMI to increase the amount of blanking period available to send packets or to increase the pixel clock to meet the minimum TMDS clock rate of 25 MHz. The ADV8003 offers three choices for the user to implement pixel repetition in the Tx core. -
Page 256: Video Related Packets And Infoframes
ADV8003 Hardware Manual pr_mode[1:0], TX2 Main Map, Address 0xF43B[6:5] This signal is used to specify the pixel repetition mode selection. This should be set to 00 unless a non CEA-861 standard video resolution must be supported. Function pr_mode[1:0] Description 00 ... -
Page 257: Mpeg Infoframe
InfoFrame. The transmission of MPEG InfoFrames can be enabled by setting the mpeg_pkt_en bit. When the transmission of MPEG InfoFrames is enabled, the ADV8003 transmits an MPEG InfoFrame once every two video fields. Table 56 provides a list of registers that can be used to configure MPEG InfoFrames. -
Page 258: Gamut Metadata
Table 57. The user can enable the transmission of GMP to the downstream sink by setting the gm_pkt_en bit. When the transmission of GMP is enabled, the ADV8003 transmits a GMP once every two video fields. Rev. B, August 2013... -
Page 259: Figure 88: I C Write Timing If Gmp Data
ADV8003 Hardware Manual The ADV8003 transmits the GMP data starting 400 pixel clock cycles after the leading edge of VSync. In order to avoid corrupting the GMP data during transmission, it is recommended that the user synchronizes all I C writes to the GMP registers so that the write begins 512 pixel clock cycles after the VSync leading edge. -
Page 260: Audio Setup
6.11.1. Audio Architecture The ADV8003 is capable of receiving audio data in I2S, SPDIF, DSD or High Bit Rate (HBR) formats. When the input audio is captured from the audio input pins, it is then converted into audio packets for transmission over the HDMI output interface. -
Page 261: Audio Configuration
ADV8003 Hardware Manual AUD_IN[5] DSD.5/LRCLK DSD.5/LRCLK LRCLK LRCLK SPDIF 6.11.2. Audio Configuration The audio_input_sel[2:0], audio_mode[1:0], i2s_format[1:0] fields must be used to configure the Tx core according to the incoming audio input. Refer to Figure 89 Figure 95 for more information on the audio timing formats. -
Page 262: Table 59: Valid Configuration For Audio_Mode[1:0]
ADV8003 Hardware Manual Function mclk_ratio[1:0] Description 128*fs 01 256*fs 384*fs 512*fs mclk_en, TX2 Main Map, Address 0xF40B[5] This bit is used to select the audio master clock that is used by the audio block. Function mclk_en Description 0 ... -
Page 263: I2S Audio
I2S Audio The ADV8003 can receive up to four stereo channels of I2S audio at up to a 192 kHz sampling rate. The number of I2S channels the Tx processes can be selected with audioif_cc[2:0]. The selection of the active I2S channels is done via the i2s_en[3:0] field. - Page 264 The ADV8003 can also receive an I2S stream in both 64-bit and 32-bit modes, so either 32- or 16-bit clock (that is, the signal input through SCLK pin) edges or cycles per channel are valid. The ADV8003 will adapt to 32- or 64-bit modes automatically,...
- Page 265 ADV8003 Hardware Manual Function audioif_cc[2:0] Description 000 Refer to stream header 2 channels 3 channels 4 channels 5 channels 6 channels 7 channels 8 channels i2s_en[3:0], TX2 Main Map, Address 0xF40C[5:2] This signal is used to enable the I2S pins.
- Page 266 ADV8003 Hardware Manual Function subpkt0_l_src[2:0] Description 000 I2S[0], left channel I2S[0], right channel I2S[1], left channel I2S[1], right channel I2S[2], left channel I2S[2], right channel I2S[3], left channel I2S[3], right channel subpkt0_r_src[2:0], TX2 Main Map, Address 0xF40E[2:0] This signal is used to specify the source of sub packet 0, right channel.
- Page 267 ADV8003 Hardware Manual subpkt2_l_src[2:0], TX2 Main Map, Address 0xF410[5:3] This signal is used to specify the source of sub packet 2, left channel. Function subpkt2_l_src[2:0] Description I2S[0], left channel I2S[0], right channel I2S[1], left channel I2S[1], right channel 100 ...
-
Page 268: Figure 89: Iec60958 Sub Stream
ADV8003 Hardware Manual Function subpkt3_r_src[2:0] Description I2S[0], left channel I2S[0], right channel I2S[1], left channel I2S[1], right channel I2S[2], left channel I2S[2], right channel I2S[3], left channel 111 I2S[3], right channel i2s_32bit_mode, TX2 Main Map, Address 0xF442[3] (Read Only) This bit is used to readback the I2S mode detection. -
Page 269: Figure 90: Aes3 Stream Format Input To Adv8003
Block Start Flag Figure 90: AES3 Stream Format Input to ADV8003 LRCLK LEFT RIGHT SCLK DATA 32 Clock Slots 32 Clock Slots Figure 91: Timing of Standard I2S Stream Input to ADV8003 LRCLK LEFT RIGHT SCLK DATA MSB-1 MSB-1 MSB extended... -
Page 270: Spdif Audio
The ADV8003 is capable of accepting SPDIF with or without an audio master clock input to through the input pin MCLK. When the ADV8003 does not receive an audio master clock, the ADV8003 uses the bit clock input via the SCLK pin to internally generate an audio master clock and determine the CTS value. -
Page 271: Dsd Audio
DSD Audio The ADV8003 uses 1-bit Audio Sample packets to transmit DSD audio data across the HDMI link to the downstream sink. The ADV8003 supports up to six channels of DSD data which can be input onto six data lines clocked by the signal input to DSD_CLK. -
Page 272: N And Cts Parameters
Note: When the HBR input stream is coming from an ADI HDMI Rx device or from the Rx section of the ADV8003, the fields listed above are set to the respective default values. Since there is no standard for chip to chip HBR transfer, different settings may be required to map the HBR stream input to the Tx core and a non ADI HDMI Rx device. -
Page 273: N Parameter
Equation 23: Relationship Between N and CTS 6.11.3.3. Recommended N and Expected CTS Values The recommended values of N for several standard pixel clocks are given in Table 62 Table The ADV8003 has two modes for CTS generation. Rev. B, August 2013... -
Page 274: Table 62: Recommended N And Expected Cts Values For 32 Khz Audio
Automatic mode is good for incoherent audio or video, where there is no simple integer ratio between the audio and video clock. The 20-bit n value used by the Tx core of the ADV8003 can be programmed in the n[19:0] field. -
Page 275: Audio Sample Packets
ADV8003 Hardware Manual Table 63: Recommended N and Expected CTS Values for 44.1 kHz and Multiples 44.1kHz 88.2 kHz 176.4 kHz Pixel Clock (MHz) 25.2 / 1.001 7007 31250 14014 31250 28028 31250 25.2 6272 28000 12544 28000 25088 28000... - Page 276 Audio Sample packets sent across the HDMI link to the downstream sink and corresponding ADV8003 fields located in the Tx Main register map. Note that the mapping shown in...
- Page 277 ADV8003 Hardware Manual Function clk_acc[1:0] Description 00 Level II - normal accuracy +/-1000 x 10^-6 Level I - high accuracy +/- 50 x 10^-6 Level III - variable pitch shifted clock Reserved category_code[7:0], TX2 Main Map, Address 0xF413[7:0] This register is used to set the channel status category code. Refer to the IEC 60958-3 specification.
-
Page 278: Table 65: I S Channel Status Adv8003 Register Map Location Of Fixed Value
ADV8003 Hardware Manual Table 65: I S Channel Status ADV8003 Register Map Location of Fixed Value Channel Status Channel Status Bit Name Main Map Bit Location or Fixed Main Map Bit Name or Fixed Value Value Consumer use 0xEC12[6] channel_status[0]... -
Page 279: Figure 97: Definition Of Channel Status Bits 20 To 23
ADV8003 Hardware Manual contain information for channels 1 and 2. If audioif_cc[2:0] is set to 0b011, indicating four channels, the layout bit will be 1; sample_present.sp0 will be 1, sample_present.sp1 will be 1, sample_present.sp2 will be 0, and sample_present.sp2 will be 0. -
Page 280: Audio Infoframe
The ADV8003 can be configured to transmit audio InfoFrame by setting audioif_pkt_en to 1. When the transmission of audio InfoFrame is enabled, the ADV8003 transmits an audio InfoFrame once every two video fields. Table 66 provides the list of registers that can be used to configure audio InfoFrames. -
Page 281: Isrc Packet
The ADV8003 can be configured to transmit ISRC packet by setting isrc_pkt_en to 1. When the transmission of an ISRC packet is enabled, the ADV8003 transmits an ISRC packet once every two video fields. Table 68 Table 69 provide the list of registers that can be used to configure ISRC packets. -
Page 282: Table 68: Isrc1 Packet Configuration Registers
ADV8003 Hardware Manual isrc_pkt_en, TX2 Main Map, Address 0xF440[3] This bit is used to enable the ISRC Packet. Function isrc_pkt_en Description 0 Disabled Enabled Table 68: ISRC1 Packet Configuration Registers Packet Map Access Type Field Name Default Value Byte Name... -
Page 283: Edid Handling
DDC lines, TXDDC_SCL and TXDDC_SDA. This EDID/HDCP controller begins buffering segment 0 of the downstream sink EDID once the sink HPD is detected and the Tx core of the ADV8003 is powered up. The system can request additional segments by programming the EDID segment pointer edid_segment[7:0]. -
Page 284: Additional Segments
EDID storage device such as EEPROM, RAM, and so on. The ADV8003 is capable of accessing up to 256 segments from EDID of the sink as allowed by the EDID specification. By writing the desired segment number to the... -
Page 285: Edid_Tries Control
0. This could be used if a sink asserts high its HPD signal before the DDC bus is ready, resulting in several NACKs as the ADV8003 attempts to read the EDID. edid_tries[3:0], TX2 Main Map, Address 0xF4C9[3:0] This signal is used to control the number of times that the EDID read will be attempted if unsuccessful. -
Page 286: Multiple Sinks And No Upstream Devices
6.13.2. Multiple Sinks and No Upstream Devices When connecting the ADV8003 as a source to an HDMI input of a repeater, it is necessary to read all BKSVs from downstream devices. These BKSVs must be checked against a revocation list, which will be provided on the source content. -
Page 287: Table 70: Ksv Fields Accessed From Edid Map
ADV8003 Hardware Manual Table 70: KSV Fields Accessed From EDID Map KSV Number Field Name Register Addresses bksv0_byte_0[7:0] 0xEE00[7:0] byte 0 bksv0_byte_1[7:0] 0xEE01[7:0] byte 1 bksv0_byte_2[7:0] 0xEE02[7:0] byte 2 bksv0_byte_3[7:0] 0xEE03[7:0] byte 3 bksv0_byte_4[7:0] 0xEE04[7:0] byte 4 bksv1_byte_0[7:0] 0xEE05[7:0] byte 0... -
Page 288: Software Implementation
4. At this time, the last host controller should be used to compare the BKSV list read from the sink with the revocation list. Once the host controller has verified none of the BKSVs read from the sink are revoked, the ADV8003 can be configured to send content down to the sink. -
Page 289: Figure 99: Hdcp Software Implementation
ADV8003 Hardware Manual START Set HDCP Request Bit HDCP_DESIRED to 1 Wait For BKSV ready interrupt Read BKSVs From Registers Tx EDID map Clear BKSV Ready Flag. Set BKSV_FLAG_INT to If HDMI Tx is part Is Sink Wait for Controller... -
Page 290: Av Mute
Tx. It requests the function from the sink device. The best way to avoid sending unauthorized audio and video is to not send data to the Tx core of the ADV8003 until authentication between the ADV8003 and the downstream sink is complete. -
Page 291: Charge Injection Settings
Description 0 Auto Manual override To increase the noise immunity of the ADV8003 ARC Rxs, it is recommended to enable the input hysteresis block on both blocks via tx1_arc_bias_hyst_adj and tx2_arc_bias_hyst_adj. tx1_arc_bias_hyst_adj, IO Map, Address 0x1A88[1] This bit is used to control the addition of hysteresis to the TX1 ARC. - Page 292 ADV8003 Hardware Manual Clock Charge Data Charge 0xECE9[7:0] 0xECF7[7:6] 0xECEC[7:0] 0xECF7[5:4] Injection Injection 00010100 00010100 10001100 10001100 00110100 00110100 11001100 11001100 10011100 10011100 11101100 11101100 01101100 01101100 11111100 11111100 11111100 11111100 11111100 11111100 Rev. B, August 2013...
-
Page 293: Consumer Electronics Control
Figure 100: CEC Module Block Diagram Note: The dual transmitter variants of ADV8003 are ADV8003KBCZ-8/7 and ADV8003KBCZ-8C/7C. The single transmitter variants of ADV8003 are ADV8003KBCZ-8B/7B. The ADV8003KBCZ-7T does not feature any HDMI transmitters. Each HDMI transmitter features a dedicated CEC master. -
Page 294: Main Controls
ADV8003 Hardware Manual 7.1. MAIN CONTROLS This section describes the main controls for the CEC module. power_mode[1:0], TX2 CEC Map, Address 0xF84E[1:0] This signal is used to set the power mode of the CEC controller. Function power_mode[1:0] Description 00 ... - Page 295 Transmission mode enabled and message transmission started The ADV8003 features three status bits related to the transmission of CEC messages. The events that set these bits are mutually exclusive, that is, only one of the three events can occur during any given message transmission.
-
Page 296: Cec Receive Section
ADV8003 Hardware Manual Function cec_tx_retry_timeout_i Description 0 Interrupt not active Interrupt active. CEC controller is indicating that the TX retry timeout has expired tx_nack_counter[3:0], TX2 CEC Map, Address 0xF814[3:0] (Read Only) The signal is used to specify the number of times that the NACK error condition was encountered while trying to send the current message. -
Page 297: Receive Buffers
Receive Buffers The ADV8003 features three frame buffers which allow the Rx to receive up to three messages before the host processor needs to read a message out. When three messages are received, no further message reception is possible until the host reads at least one message. - Page 298 ADV8003 Hardware Manual Function use_all_bufs Description Use only buffer 0 to store CEC frames (legacy mode) 1 Use all three buffers to store the CEC frames (non-legacy mode) For each of the frame buffers there is a corresponding two-bit time stamp and a raw flag as described below.
-
Page 299: Table 73: Cec Incoming Frame Buffer 0 Registers
ADV8003 Hardware Manual an interrupt is generated to alert the host processor to the fact that a message was received. When all three frame buffers are full the receive module can no longer receive CEC messages and will not acknowledge any new messages (other than polling messages). -
Page 300: Cec Message Reception Overview
ADV8003 Hardware Manual Table 75: CEC Incoming Frame Buffer 2 Registers Register Name CEC Map Description Address cec_buf2_rx_frame_header[7:0] 0x65 Header of message in frame buffer 2 cec_buf2_rx_frame_data0[7:0] 0x66 Byte 0 of message in frame buffer 2 cec_buf2_rx_frame_data1[7:0] 0x67 Byte 1 of message in frame buffer 2... -
Page 301: Antiglitch Filter Module
ADV8003 Hardware Manual timestamp of 0b10 is assigned to receive buffer 0 to show that it contains the second received message. If the corresponding interrupt mask bit is set, cec_rx_ready_int[2:0] goes high and an interrupt is generated to alert the host processor that a message was received. -
Page 302: Typical Operation Flow
This section describes the algorithm that should be implemented in the host processor controlling the CEC module. 7.5.1. Initializing CEC Module Figure 101 shows the flow that can be implemented in the host processor controlling the ADV8003 in order to initialize the CEC module. Start Set POWER_MODE to 01 Enable... -
Page 303: Figure 102: Using Cec Module As Initiator
ADV8003 Hardware Manual Start Write the outgoing CEC command into the outgoing message registers (CEC Map Reg 0x00 to 0x0F) Set TX_FRAME_LENGTH According to the number of bytes in the outgoing message Set TX_ENABLE to 1 CEC_TX_ARBITRATION _LOST_INT CEC_TX_READY_INT CEC_TX_RETRY_TIMEOUT_INT... -
Page 304: Using Cec Module As Follower
ADV8003 Hardware Manual 7.5.3. Using CEC Module as Follower Figure 103 shows the algorithm that can be implemented in the host processor controlling the ADV8003 in order to use the CEC module as a follower. START (wait for interrupt) CEC_RX_READY_INT... -
Page 305: Low Power Cec Message Monitoring
7.6. LOW POWER CEC MESSAGE MONITORING The ADV8003 can be programmed to monitor the CEC line for messages which contain specific, user-programmable opcodes. These are referred to as “wake_opcodes” as they allow the system to go into a low power or sleep mode and be woken up when an opcode of interest is received without the host processor having to check each received message. - Page 306 ADV8003 Hardware Manual Function wake_opcode3[7:0] Description 00000100 Image view on xxxxxxxx User specified OPCODE to respond to wake_opcode4[7:0], TX2 CEC Map, Address 0xF87B[7:0] This register is used to specify the CEC_WAKE_OPCODE4. This value can be set to a CEC opcode that requires a response. On receipt of this opcode the Rx generates an interrupt that can be used to alert the system that a CEC opcode of interest has been received and requires a response.
-
Page 307: Video Encoder
The ADV8003 encoder core is capable of supporting independent SD and ED/HD video outputs, and also both SD and ED/HD video in simultaneous mode. The data coming either from the VSP section or directly from the ADV8003 front-end input, is input to the SD encoder through two 8/10/12-bit SDR buses; the ED/HD encoder is accessed through three 8/10/12-bit SDR buses. -
Page 308: Figure 105: Simplified View Of Adv8003 Encoder Block
Table 76 lists the possible input standards supported by the ADV8003 encoder core. Note that if using the ADV8003 de-interlacer and/or scaler, the input standard of the encoder must be set to that of the output of the VSP section. If bypassing the VSP section, the user should set this to the standard of the external input video. - Page 309 1), the ADV8003 encoder core can automatically identify an NTSC or a PAL B/D/G/H/I input stream. The ADV8003 encoder core is also configured to correctly encode the identified standard. The SD standard bits (sd_enc_ip_mode[1:0]) and the subcarrier frequency registers are not updated to reflect the identified standard; all registers retain their default or user defined values.
-
Page 310: Output Configuration
ADV8003 Hardware Manual Table 76: Standards Directly Supported by ADV8003 Encoder Processor Active Frame Standard Resolution Rate (Hz) 720 × 240 59.94 720 × 288 720 × 480 29.97 ITU-R BT.601/656 720 × 576 ITU-R BT.601/656 720 × 483 59.94 SMPTE 293M 720 ×... - Page 311 ADV8003 Hardware Manual Function dac1_sel[2:0] Description CVBS or Black Burst Luma Chroma 3 Pb/B Pr/R Core Bypass DAC DFT DDS Eval DFT dac2_sel[2:0], Encoder Map, Address 0xE42B[6:4] This signal selects the data that is supplied to DAC 5. Function...
-
Page 312: Additional Design Features
8.4. ADDITIONAL DESIGN FEATURES This section outlines the various design features of the encoder which can be used to improve the overall video quality and the ADV8003 performance in a system. Many of these functions are optional and should be set depending on a user’s application. -
Page 313: Subcarrier Frequency Lock (Sfl) Mode
ADI decoder (for example, ADV784x) which is used to lock the subcarrier frequency. This enables the ADV8003 encoder to stay locked to a video pixel clock which drifts over the time (this happens with poor video sources like VCRs). -
Page 314: Vertical Blanking Interval
Vertical Blanking Interval The ADV8003 encoder core is able to accept input data that contains VBI data (such as CGMS, WSS, VITS) in SD, ED, and HD modes. If VBI is disabled, VBI data is not present at the output and the entire VBI is blanked. These control bits are valid in all master and slave timing modes. -
Page 315: Programming The Fsc
The ADV8003 encoder core supports an SD noninterlaced mode. Using this mode, progressive inputs at twice the frame rate of NTSC and PAL (240p/59.94 Hz and 288p/50 Hz respectively) can be input into the ADV8003 encoder. If the user selects the input to be 240p or 288p, sd_non_interlaced must be set correspondingly. -
Page 316: Figure 106: Sd Luma Ssaf Filter, Programmable Responses
ADV8003 Hardware Manual Filter Pass-Band Ripple (dB) 3 dB Bandwidth (MHz) Luma Notch PAL 3.1/5.6/6.4 Luma SSAF 0.04 6.45 Luma CIF 0.127 3.02 Luma QCIF Monotonic Chroma 0.65 MHz Monotonic 0.65 Chroma 1.0 MHz Monotonic Chroma 1.3 MHz 0.09 1.395 Chroma 2.0 MHz... -
Page 317: Figure 107: Sd Luma Ssaf Filter, Programmable Gains
ADV8003 Hardware Manual –1 FREQUENCY (MHz) Figure 107: SD Luma SSAF Filter, Programmable Gains –1 –2 –3 –4 –5 FREQUENCY (MHz) Figure 108: SD Luma SSAF Filter, Programmable Attenuation peak_en, Encoder Map, Address 0xE487[4] This bit is used to enable the SD SSAF filter gain. -
Page 318: Ed/Hd Filters
8.4.7.2. ED/HD Filters The ADV8003 encoder core also includes a sinc compensation filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in ED/HD mode. The benefit of the filter is illustrated in... -
Page 319: Ed/Hd Test Pattern Generator
ED/HD Test Pattern Generator ADV8003 is able to internally generate ED/HD black bar, uniform background color or hatch test patterns. It is not possible to output a color bar test pattern while EH/HD video is being routed through the encoder. This test pattern can be enabled using... -
Page 320: Table 80: Sample Color Values For Eia 770.2/Eia770.3 Ed/Hd Output Standard Selection
ADV8003 Hardware Manual Function hdtv_tp_en Description 0 ED/HD test pattern off ED/HD test pattern on The values for the luma (Y) and the color difference (Cr and Cb) signals used to obtain white, black, and saturated primary and complementary colors conform to the ITU-R BT.601-4 standard. -
Page 321: Color Space Conversion Matrix
The input to the encoder block on the ADV8003 should always be in a YCbCr color space. If an RGB color space is present at the input pins, the CSC on the I/O block of the ADV8003 can be used to convert it to YCbCr. It is possible, however, to convert from YCbCr to an RGB stream in the encoder. -
Page 322: Programming The Csc Matrix
ADV8003 Hardware Manual On powerup, the CSC matrix is programmed with the default values shown in Table Table 81: ED/HD Manual CSC Matrix Default Values Register Default 0x03 0x03 0x04 0xF0 0x05 0x4E 0x06 0x0E 0x07 0x24 0x08 0x92 0x09... - Page 323 ADV8003 Hardware Manual scale_ycbcr_en, Encoder Map, Address 0xE487[0] This bit is used to enable the SD luma and color scale control feature. Function scale_ycbcr_en Description Enabled 0 Disabled When enabled, three 10-bit registers (SD Y scale, SD Cb scale, and SD Cr scale) control the scaling of the SD Y, Cb, and Cr output levels.
-
Page 324: Sd Hue Adjust Control
Register 0xE4A0 contains the bits required to vary the hue of the video data, that is, the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV8003 encoder provides a range of ±22.5° in increments of 0.17578125°. -
Page 325: Sd Brightness Detect
8.4.13. SD Brightness Detect The ADV8003 encoder core allows the user to monitor the brightness level of the incoming video data. This feature is used to monitor the average brightness of the incoming Y signal on a field-by-field basis. The information is read from the I C and, based on this information, the color saturation, contrast, and brightness controls can be adjusted, for example, to compensate for very dark pictures. -
Page 326: Double Buffering
ADV8003 Hardware Manual Function setup[6:0] Description 0x00 SD brightness value Table 82: Sample Brightness Control Values Setup Level (NTSC) with Pedestal Setup Level (NTSC) Without Pedestal Setup Level (PAL) Brightness Control Value setup[6:0] 22.5 IRE 15 IRE 15 IRE... -
Page 327: Programmable Dac Gain Control
ADV8003 Hardware Manual Double buffering can be activated on the following SD functions: the SD gamma A and gamma B curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD closed captioning, and SD Macrovision bits (Reg 0xE4E0, Bits [5:0]). -
Page 328: Table 83: Dac Gain Control
ADV8003 Hardware Manual Function dac4to6_tuning[7:0] Description 11000000 -7.5% 11000001 -7.382% 11000010 -7.364% … 11111111 -0.018% 00000000 00000001 0.018% 00000010 0.036% … 00111111 +7.382% 01000000 +7.5% dac1to3_tuning[7:0], Encoder Map, Address 0xE40B[7:0] This register is used to set the gain for DACs 1-3 output voltage. -
Page 329: Gamma Correction
ADV8003 Hardware Manual 8.4.17. Gamma Correction Generally, gamma correction is applied to compensate for the nonlinear relationship between the signal input and the output brightness level (as perceived on a CRT). It can also be applied wherever nonlinear processing is used. -
Page 330: Ed/Hd Gamma Correction
ADV8003 Hardware Manual Where the sum of each equation is rounded to the nearest integer, these must then all be converted to hex. The gamma curves in Figure 114 Figure 115 are examples only; any user defined curve in the range from 16 to 240 is acceptable. -
Page 331: Sd Gamma Correction
ADV8003 Hardware Manual Table 84: ED/HD Gamma Curve A Curve Type Point Register Address ED/HD Gamma Curve A (A0 – Point 24) 0xE444 ED/HD Gamma Curve A (A1 – Point 32) 0xE445 ED/HD Gamma Curve A (A2 – Point 48) -
Page 332: Ed/Hd Sharpness Filter And Adaptive Filter Controls
Gamma correction curve A Gamma correction curve B 8.4.18. ED/HD Sharpness Filter and Adaptive Filter Controls There are three filter modes available on the ADV8003 encoder block: a sharpness filter mode and two adaptive filter modes. 8.4.18.1. ED/HD Sharpness Filter Mode... -
Page 333: Figure 116: Ed/Hd Sharpness And Adaptive Filter Control Block
ADV8003 Hardware Manual SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK INPUT SIGNAL STEP FREQUENCY (MHz) FREQUENCY (MHz) FILTER A RESPONSE (Gain Ka) FREQUENCY (MHz) FILTER B RESPONSE (Gain Kb) FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH Ka = 3 AND Kb = 7 Figure 116: ED/HD Sharpness and Adaptive Filter Control Block To enable the ED/HD sharpness filter, the following bit must be written to. -
Page 334: Ed/Hd Adaptive Filters
ADV8003 Hardware Manual Function kb[3:0] Description 0000 Gain B 0 0001 Gain B +1 … 0111 Gain B +7 1000 Gain B -8 … 1110 Gain B -2 1111 Gain B -1 ka[3:0], Encoder Map, Address 0xE440[3:0] This signal is used to configure the ED/HD sharpness filter gain, value A. - Page 335 ADV8003 Hardware Manual Function thold_b[7:0] Description Default 0x00 thold_c[7:0], Encoder Map, Address 0xE45D[7:0] This register is used to set the ED/HD adaptive filter threshold C. Function thold_c[7:0] Description Default 0x00 The edges can then be attenuated with the settings in the ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers. Refer to the...
-
Page 336: Ed/Hd Adaptive Filter Modes
ADV8003 Hardware Manual Function fil_resp_bb[3:0] Description 0000 Gain B 0 0001 Gain B +1 0111 Gain B +7 1000 Gain B -8 1110 Gain B -2 1111 Gain B -1 fil_resp_cb[3:0], Encoder Map, Address 0xE45A[7:4] This signal is used to set the adaptive filter gain 3 for the ED/HD standard. This is value B. -
Page 337: Ed/Hd Sharpness Filter And Adaptive Filter Application Examples
ADV8003 Hardware Manual Function adapt_bc Description 0 Mode A Mode B 8.4.18.4. ED/HD Sharpness Filter and Adaptive Filter Application Examples Sharpness Filter Application The ED/HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings in... -
Page 338: Figure 118: Input Signal To Ed/Hd Adaptive Filter
ADV8003 Hardware Manual Register Register Setting 0xE431 0x81 0xE435 0x80 0xE440 0x00 0xE458 0xAC 0xE459 0x9A 0xE45A 0x88 0xE45B 0x28 0xE45C 0x3F 0xE45D 0x64 Figure 118: Input Signal to ED/HD Adaptive Filter The effects of selecting between the two adaptive filter modes (using... -
Page 339: Sd Digital Noise Reduction
8.4.19. SD Digital Noise Reduction The ADV8003 encoder block offers a feature for digital noise reduction (DNR). DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute value of the filter output is compared to a programmable threshold value (DNR threshold control). -
Page 340: Coring Gain Border
ADV8003 Hardware Manual Function dnr_en Description Enabled 0 Disabled 8.4.19.1. Coring Gain Border dnr_coring_gain_a[3:0] is the gain factor applied to border areas (refer to Figure 127 for more information on border areas). In DNR mode, the range of gain values is 0 to -1 in decrements of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. -
Page 341: Dnr Threshold
ADV8003 Hardware Manual dnr_coring_gain_b[3:0], Encoder Map, Address 0xE4A3[3:0] This signal is used to configure the coring gain data (in Digital Noise Reduction (DNR) mode, the values in brackets apply). Function dnr_coring_gain_b[3:0] Description 0000 No gain 0001 +1/16 [−1/8] 0010 +2/16 [−2/8]... -
Page 342: Block Size Control
ADV8003 Hardware Manual Function blk_border_2 Description 0 2 pixels 4 pixels 8.4.19.5. Block Size Control dnr_mpeg_1 is used to select the size of the data blocks to be processed. Setting the block size control function to 1 defines a 16 pixel × 16 pixel data block, and 0 defines an 8 pixel ×... -
Page 343: Dnr Block Offset Control
8.4.19.9. SD Active Video Edge Control The ADV8003 encoder core is able to control fast rising and falling signals at the start and end of active video in order to minimize ringing artifacts. When the active video edge control feature is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible. -
Page 344: Figure 126: Example Of Video Output With Sd Active Video Edge Control Disabled
ADV8003 Hardware Manual VOLTS IRE:FLT L135 –50 Figure 126: Example of Video Output with SD Active Video Edge Control Disabled VOLTS IRE:FLT L135 –50 –2 Figure 127: Example of Video Output with SD Active Video Edge Control Enabled slope_en, Encoder Map, Address 0xE482[7] This bit is used to enable the SD active video edge control. -
Page 345: Vertical Blanking Interval
8.5. VERTICAL BLANKING INTERVAL The ADV8003 is capable of accepting input VBI data (for example, CGMS, WSS, and CCAP) in SD, ED and HD modes. If VBI is disabled, for SD mode, see vbi_open, for HD mode, see vbi_data_en. VBI data is not present at the encoder output and the entire VBI is blanked. -
Page 346: Dac Configurations
Video Output Buffer and Optional Output Filter A video buffer is necessary on the DAC outputs to match the 300Ω output impedance of the ADV8003 encoder output to the 75Ω input impedance of the sink device. ADI produces a range of op amps suitable for this application, for example, the AD8061. For more information about line driver buffering circuits, refer to the relevant op amp datasheet. -
Page 347: Figure 129: Example Of Output Filter For Ed, 8× Oversampling
ADV8003 Hardware Manual 4.7µH OUTPUT 75Ω 600Ω 6.8pF OUTPUT 600Ω 6.8pF 560Ω 560Ω Figure 129: Example of Output Filter for ED, 8× Oversampling OUTPUT 390nH 75Ω 300Ω OUTPUT 33pF 33pF 75Ω 500Ω 500Ω Figure 130: Example of Output Filter for HD, 4× Oversampling CIRCUIT FREQUENCY RESPONSE –30... -
Page 348: Figure 133: Output Filter Plot For Hd, 4× Oversampling
ADV8003 Hardware Manual CIRCUIT FREQUENCY RESPONSE PHASE (Degrees) MAGNITUDE (dB) –10 GROUP DELAY (Seconds) –20 –30 –40 –40 –120 –50 –200 FREQUENCY (MHz) Figure 133: Output Filter Plot for HD, 4× Oversampling Rev. B, August 2013... -
Page 349: Interrupts
9. INTERRUPTS The ADV8003 has a comprehensive set of interrupt registers located in the IO Map and HDMI Main Maps of both the Serial Video Rx and HDMI transmitters. These interrupts can be used to indicate certain events in the Serial Video Rx section, OSD, and VSP, and also the HDMI Tx. -
Page 350: Storing Masked Interrupts
9.2.1. Introduction This section describes the interrupt support provided for the Serial Video Rx on the ADV8003. The Serial Video Rx interrupts are OR’ d together and connected to the ADV8003 INT2 pin. The ADV8003 Serial Video Rx interrupt architecture provides the following types of bits: •... -
Page 351: Figure 134: Level And Edge-Sensitive Raw, Status And Interrupt Generation
ADV8003 Hardware Manual edge_sensitive_int_raw, IO, Address 0xXX (Read Only) This readback indicates the status of the edge sensitive interrupt. When set to 1, it indicates that an event has occured. Once set, this bit remains high until the interrupt is cleared via edge_sensitive_int_clr. -
Page 352: Figure 135: Avi_Info_Raw And Avi_Info_St Timing
ADV8003 Hardware Manual AVI infoFrame Detection Internal Flag No AVI AVI InfoFrame InfoFrame Detected Detected AVI_INFO_RAW AVI_INFO_ST AVI_INFO_CLR AVI_INFO_CLR set to 1 set to 1 Time taken by Time taken by the CPU to clear the CPU to clear AVI_INFO_ST... - Page 353 ADV8003 Hardware Manual level_sensitive_int_st, IO, Address 0xXX (Read Only) This readback indicates the latched status of the level_sensitive_int_raw signal. This bit is only valid if enabled via the corresponding INT1 interrupt mask bit. Once set, this bit remains high until the interrupt is cleared level_sensitive_int_clr.
-
Page 354: Interrupt Architecture Overview
ADV8003 Hardware Manual Function edge_sensitive_int_mb2 Description 0 Disable edge_sensitive_int detection interrupt for INT2 Enable edge_sensitive_int detection interrupt for INT2 In this section, all raw bits are classified as being triggered by either level-sensitive or edge-sensitive events, with the following understanding of the terminology. -
Page 355: Multiple Interrupt Events
All Serial Video interrupts have a set of conditions that must be taken into account for validation in the system firmware. When the ADV8003 alerts the system controller with a Serial Video interrupt, the host must check that the following validity conditions for that interrupt are met before processing that interrupt. -
Page 356: Hdmi Tx Core
9.4.1. Introduction This section describes the interrupt support provided for the HDMI Tx cores of the ADV8003. The HDMI Tx interrupts are OR’ d together and connected to the ADV8003 INT1 pin. The ADV8003 HDMI Tx interrupt architecture provides the following types of bits: •... -
Page 357: Hdmi Tx Interrupt Polarity
ADV8003 Hardware Manual Interrupt Description cec_tx_retry_timeout_int/ Used to indicate if the CEC master has failed to retransmit after the default timeout cec_tx_retry_timeout_int_en cec_rx_ready_int/ cec_rx_ready_int_en Used to indicate if a new message is present in one of the CEC Rx buffers 9.4.3. -
Page 358: Pcb Layout Recommendations
PCB LAYOUT RECOMMENDATIONS The ADV8003 is a high precision, high speed, mixed signal device. It is important to have a well laid out PCB board in order to achieve the maximum performance from the part. The following sections are a guide for designing a board using the ADV8003. -
Page 359: Power Supply Bypassing
It is recommended to use a single ground plane for the ADV8003. Careful attention must be paid to the layout of any internal power supply planes when traces run on adjacent layers – traces on a layer directly above or below a power supply layer must not cross between two power supply planes as this will impact the return current paths. -
Page 360: General Digital Inputs And Outputs
ADV8003. Special care must be taken when using a crystal circuit to generate the reference clock for the ADV8003. Small variations in reference clock frequency can impair the performance of the ADV8003. -
Page 361: Encoder Component Placement
External component placement must be carefully considered – they should be kept as far away as possible from noisy circuits, as close to the ADV8003 as possible and preferably on the same layer as the ADV8003. The R_TX1 and R_TX2 resistors and PVDD5 and PVDD6 power supplies must all be carefully laid out otherwise the HDMI transmitter performance, for example, HDMI compliance testing, may be reduced. -
Page 362: Figure 139: Power Supply Design
ADV8003 Hardware Manual 3.3V R egulator F ilter AVDD1 F ilter AVDD2 F ilter D VD D IO R/C D elay Enable AD V8003 1.8V R egulator F ilter AVDD3 F ilter CVDD1 F ilter DVDD F ilter DVDD_DDR F ilter... -
Page 363: Adv8003 Evaluation Board Schematics
ADV8003 Hardware Manual APPENDIX B ADV8003 EVALUATION BOARD SCHEMATICS Figure 141: ADV8003 Schematic – Page 1 Rev. B, August 2013... -
Page 364: Figure 142: Adv8003 Schematic
ADV8003 Hardware Manual Figure 142: ADV8003 Schematic – Page 2 Rev. B, August 2013... -
Page 365: Figure 143: Adv8003 Schematic
ADV8003 Hardware Manual Figure 143: ADV8003 Schematic – Page 3 Rev. B, August 2013... -
Page 366: Figure 144: Adv8003 Schematic
ADV8003 Hardware Manual Figure 144: ADV8003 Schematic – Page 4 Rev. B, August 2013... -
Page 367: Figure 145: Adv8003 Schematic
ADV8003 Hardware Manual Figure 145: ADV8003 Schematic – Page 5 Rev. B, August 2013... -
Page 368: Figure 146: Adv8003 Schematic
ADV8003 Hardware Manual Figure 146: ADV8003 Schematic – Page 6 Rev. B, August 2013... -
Page 369: Figure 147: Adv8003 Schematic
ADV8003 Hardware Manual Figure 147: ADV8003 Schematic – Page 7 Rev. B, August 2013... -
Page 370: Figure 148: Adv8003 Schematic
ADV8003 Hardware Manual Figure 148: ADV8003 Schematic – Page 8 Rev. B, August 2013... -
Page 371: Figure 149: Adv8003 Schematic
ADV8003 Hardware Manual Figure 149: ADV8003 Schematic – Page 9 Rev. B, August 2013... -
Page 372: Figure 150: Adv8003 Schematic
ADV8003 Hardware Manual Figure 150: ADV8003 Schematic – Page 10 Rev. B, August 2013... -
Page 373: Figure 151: Adv8003 Schematic
ADV8003 Hardware Manual Figure 151: ADV8003 Schematic – Page 11 Rev. B, August 2013... -
Page 374: Figure 152: Adv8003 Schematic
ADV8003 Hardware Manual Figure 152: ADV8003 Schematic – Page 12 Rev. B, August 2013... -
Page 375: Figure 153: Adv8003 Schematic
ADV8003 Hardware Manual Figure 153: ADV8003 Schematic – Page 13 Rev. B, August 2013... -
Page 376: Figure 154: Adv8003 Schematic
ADV8003 Hardware Manual Figure 154: ADV8003 Schematic – Page 14 Rev. B, August 2013... -
Page 377: Figure 155: Adv8003 Schematic
ADV8003 Hardware Manual Figure 155: ADV8003 Schematic – Page 15 Rev. B, August 2013... -
Page 378: Figure 156: Adv8003 Schematic
ADV8003 Hardware Manual Figure 156: ADV8003 Schematic – Page 16 Rev. B, August 2013... -
Page 379: Figure 157: Adv8003 Schematic
ADV8003 Hardware Manual Figure 157: ADV8003 Schematic – Page 17 Rev. B, August 2013... -
Page 380: Figure 158: Adv8003 Schematic
ADV8003 Hardware Manual Figure 158: ADV8003 Schematic – Page 18 Rev. B, August 2013... -
Page 381: Figure 159: Adv8003 Schematic
ADV8003 Hardware Manual Figure 159: ADV8003 Schematic – Page 19 Rev. B, August 2013... -
Page 382: Figure 160: Adv8003 Schematic
ADV8003 Hardware Manual Figure 160: ADV8003 Schematic – Page 20 Rev. B, August 2013... -
Page 383: Figure 161: Adv8003 Schematic
ADV8003 Hardware Manual Figure 161: ADV8003 Schematic – Page 21 Rev. B, August 2013... -
Page 384: Figure 162: Adv8003 Schematic
ADV8003 Hardware Manual Figure 162: ADV8003 Schematic – Page 22 Rev. B, August 2013... -
Page 385: Figure 163: Adv8003 Schematic
ADV8003 Hardware Manual Figure 163: ADV8003 Schematic – Page 23 Rev. B, August 2013... -
Page 386: Figure 164: Adv8003 Schematic
ADV8003 Hardware Manual Figure 164: ADV8003 Schematic – Page 24 Rev. B, August 2013... -
Page 387: Figure 165: Adv8003 Schematic
ADV8003 Hardware Manual Figure 165: ADV8003 Schematic – Page 25 Rev. B, August 2013... -
Page 388: Figure 166: Adv8003 Schematic
ADV8003 Hardware Manual Figure 166: ADV8003 Schematic – Page 26 Rev. B, August 2013... -
Page 389: Figure 167: Adv8003 Schematic
ADV8003 Hardware Manual Figure 167: ADV8003 Schematic – Page 27 Rev. B, August 2013... -
Page 390: Figure 168: Adv8003 Schematic
ADV8003 Hardware Manual Figure 168: ADV8003 Schematic – Page 28 Rev. B, August 2013... -
Page 391: Figure 169: Adv8003 Schematic
ADV8003 Hardware Manual Figure 169: ADV8003 Schematic – Page 29 Rev. B, August 2013... -
Page 392: Figure 170: Adv8003 Schematic
ADV8003 Hardware Manual Figure 170: ADV8003 Schematic – Page 30 Rev. B, August 2013... -
Page 393: Figure 171: Adv8003 Schematic
ADV8003 Hardware Manual Figure 171: ADV8003 Schematic – Page 31 Rev. B, August 2013... -
Page 394: Adv8003 Evaluation Board Layout
ADV8003 Hardware Manual APPENDIX C ADV8003 EVALUATION BOARD LAYOUT Figure 172: ADV8003 Layout – Page 1 Rev. B, August 2013... -
Page 395: Figure 173: Adv8003 Layout
ADV8003 Hardware Manual Figure 173: ADV8003 Layout – Page 2 Rev. B, August 2013... -
Page 396: Figure 174: Adv8003 Layout
ADV8003 Hardware Manual Figure 174: ADV8003 Layout – Page 3 Rev. B, August 2013... -
Page 397: Figure 175: Adv8003 Layout
ADV8003 Hardware Manual Figure 175: ADV8003 Layout – Page 4 Rev. B, August 2013... -
Page 398: Figure 176: Adv8003 Layout
ADV8003 Hardware Manual Figure 176: ADV8003 Layout – Page 5 Rev. B, August 2013... -
Page 399: Figure 177: Adv8003 Layout
ADV8003 Hardware Manual Figure 177: ADV8003 Layout – Page 6 Rev. B, August 2013... -
Page 400: Figure 178: Adv8003 Layout
ADV8003 Hardware Manual Figure 178: ADV8003 Layout – Page 7 Rev. B, August 2013... -
Page 401: Figure 179: Adv8003 Layout
ADV8003 Hardware Manual Figure 179: ADV8003 Layout – Page 8 Rev. B, August 2013... -
Page 402: Package Outline Drawing
ADV8003 Hardware Manual APPENDIX D PACKAGE OUTLINE DRAWING Refer to Section 1.4. Rev. B, August 2013... -
Page 403: Unused Pin List
ADV8003 Hardware Manual APPENDIX E UNUSED PIN LIST Location Mnemonic Type Description if Unused Pin Type OSD_IN[23]/EXT_DIN[7] OSD video Connect this pin to ground through a Bi-directional digital IO input/ 4.7kΩ resistor. miscellaneous digital OSD_DE OSD video Connect this pin to ground through a... - Page 404 ADV8003 Hardware Manual Location Mnemonic Type Description if Unused Pin Type 4.7kΩ resistor. AUD_IN[3] Audio input Connect this pin to ground through a Digital input 4.7kΩ resistor. Connect this pin to ground through a Digital input 4.7kΩ resistor. ARC1_OUT Audio output...
- Page 405 ADV8003 Hardware Manual Location Mnemonic Type Description if Unused Pin Type Ground. No connect Float this pin. Digital output No connect Float this pin. Digital output RX_HPD Rx input Float this pin. Digital output AVDD1 Power Serial Video Rx Inputs Analog Supply (3.3 V).
- Page 406 ADV8003 Hardware Manual Location Mnemonic Type Description if Unused Pin Type output DAC2 Analog video Float this pin. Analog output output OSD_IN[13]/VBI_SCK OSD video Connect this pin to ground through a Bi-directional digital IO input/ 4.7kΩ resistor. miscellaneous digital OSD_IN[14]/VBI_MOSI...
- Page 407 ADV8003 Hardware Manual Location Mnemonic Type Description if Unused Pin Type Ground. Ground. Ground. ELPF1 Miscellaneous This pin must be connected. analog ELPF2 Miscellaneous This pin must be connected. analog Ground. AVDD3 Power HDMI Analog Power Supply (1.8 V). OSD_IN[1]...
- Page 408 ADV8003 Hardware Manual Location Mnemonic Type Description if Unused Pin Type DVDD Power Digital Power Supply (1.8 V). DDC1_SDA HDMI Tx1 Float this pin. Digital output Ground. TX1_1+ HDMI Tx1 Float this pin. Digital output TX1_1− HDMI Tx1 Float this pin.
- Page 409 ADV8003 Hardware Manual Location Mnemonic Type Description if Unused Pin Type P[29] Digital video Connect this pin to ground through a Bi-directional digital IO input 4.7kΩ resistor. P[30] Digital video Connect this pin to ground through a Bi-directional digital IO input 4.7kΩ...
- Page 410 ADV8003 Hardware Manual Location Mnemonic Type Description if Unused Pin Type P[20] Digital video Connect this pin to ground through a Digital input input 4.7kΩ resistor. P[21] Digital video Connect this pin to ground through a Digital input input 4.7kΩ resistor.
- Page 411 ADV8003 Hardware Manual Location Mnemonic Type Description if Unused Pin Type Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. HPD_TX2 HDMI Tx2 Float this pin. Analog input Ground. TX2_0+ HDMI Tx2 Float this pin. Digital output TX2_0−...
- Page 412 ADV8003 Hardware Manual Location Mnemonic Type Description if Unused Pin Type between this pin and ground. HEAC_2+ HDMI Tx2 Connect this pin to ground through a Bi-directional digital IO 4.7kΩ resistor. HEAC_2− HDMI Tx2 Connect this pin to ground through a Bi-directional digital IO 4.7kΩ...
- Page 413 DDR_ DQS[3] DDR interface Connect this pin to ground through a Bi-directional digital IO 4.7kΩ resistor. NC/GND For New ADV8003 Designs, Float this connect/GND pin. For Designs That Must Maintain Consistency with ADV8003, this Pin can be Grounded. DDR_A[8] DDR interface Float this pin.
- Page 414 ADV8003 Hardware Manual Location Mnemonic Type Description if Unused Pin Type AB16 DDR_DQ[12] DDR interface Connect this pin to ground through a Bi-directional digital IO 4.7kΩ resistor. AB17 DDR_DQS[1] DDR interface Connect this pin to ground through a Bi-directional digital IO 4.7kΩ...
- Page 415 ADV8003 Hardware Manual Sensitive node. Careful layout is important. The associated circuitry should be kept as close as possible to the ADV8003. Pull downs can be shared between 4 – 6 pins if desired Rev. B, August 2013...
-
Page 416: Pixel Input And Output Formats
ADV8003 Hardware Manual APPENDIX F PIXEL INPUT AND OUTPUT FORMATS Table 95: RGB Input Formats ADV8003 8-BIT DDR 10-BIT DDR 12-BIT DDR PIN NAME 4:2:2 4:2:2 4:2:2 4:4:4 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:4:4 4:4:4 4:4:4 4:4:4 4:4:4 4:4:4... - Page 417 ADV8003 Hardware Manual OSD_IN.3 B1.7 OSD_IN.2 B1.6 OSD_IN.1 B1.5 OSD_IN.0 B1.4 P.35 B1.3 P.34 B1.2 P.33 B1.1 P.32 B1.0 P.31 R1.7 P.30 R1.6 P.29 R1.5 P.28 R1.4 P.27 R1.3 P.26 R1.2 P.25 R1.1 P.24 R1.0 P.23 G2.7 Main P.22 G2.6 P.21...
-
Page 418: Table 96: Ycbcr Input Formats
ADV8003 Hardware Manual R2.7 R2.6 R2.5 R2.4 R2.3 R2.2 R2.1 R2.0 Table 96: YCbCr Input Formats ADV8 8-BIT 12-BIT 8-BIT DDR 10-BIT DDR 12-BIT DDR 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:4:4 4:2:2 4:2:2 4:2:2 4:2:2 4:4:4 4:4:4 4:4:4 4:4:4 4:4:4... - Page 419 ADV8003 Hardware Manual Cb3/ Cb5/ OSD_ Cr3,Y Cr5,Y Cb7/Cr Cb3, Cb5, Cb7, IN.19 7,Y7 Cb2/ Cb4/ OSD_ Cr2,Y Cr4,Y Cb6/Cr Cb2, Cb4, Cb6, IN.18 6,Y6 Cb1/ Cb3/ OSD_ Cr1,Y Cr3,Y Cb5/Cr Cb1, Cb3, Cb5, IN.17 5,Y5 Cb0/ Cb2/ OSD_ Cr0,Y...
- Page 420 ADV8003 Hardware Manual Cb1. OSD_ Cb0, Y1.0 IN.0 Cb1. Cb.1 Cb.7 Cb.9 P.35 Cr11 Cb1. Cb.1 Cb.6 Cb.8 P.34 Cr10 Cb1. Cb.5 Cb.7 Cb.9 P.33 Cb1. Cb.4 Cb.6 Cb.8 P.32 Cr1.7 Cb.3 Cb.5 Cb.7 P.31 Cr1.6 Cb.2 Cb.4 Cb.6 P.30 Cr1.5...
- Page 421 ADV8003 Hardware Manual Cb1/ Cb3/ Cr1,Y Cr3,Y Cb5/Cr Cb1, Cb3, Cb5, Y2.1 Y2.1 Y2.3 Y2.5 P.17 5,Y5 Cb0/ Cb2/ Cr0,Y Cr2,Y Cb4/Cr Cb0, Cb2, Cb4, Y2.0 Y2.0 Y2.2 Y2.4 P.16 4,Y4 Cb1/ Cb2. Cr1,Y Cb3/Cr Cb1, Cb3, Y2.1 Y2.3 P.15...
-
Page 422: Table 97: Alpha Blending Input Formats
ADV8003 Hardware Manual VID_ VID_ VID_ VID_CL VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ Table 97: Alpha Blending Input Formats Alpha Format OSD_DE OSD_VS OSD_CLK OSD_IN.23 OSD_IN.22 OSD_IN.21 OSD_IN.20... - Page 423 ADV8003 Hardware Manual OSD_IN.4 OSD_IN.3 OSD_IN.2 OSD_IN.1 OSD_IN.0 P.35 P.34 P.33 P.32 P.31 P.30 P.29 P.28 P.27 P.26 P.25 P.24 P.23 P.22 P.21 P.20 P.19 P.18 P.17 P.16 P.15 P.14 P.13 P.12 P.11 P.10 Rev. B, August 2013...
- Page 424 ADV8003 Hardware Manual VID_DE VID_HS VID_VS VID_CLK Rev. B, August 2013...
-
Page 425: Table 98: Rgb Ttl Output Formats
ADV8003 Hardware Manual Table 98: RGB TTL Output Formats ADV8003 PIN 24-BIT SDR 4:4:4 30-BIT SDR 4:4:4 36-BIT SDR 4:4:4 NAME OSD_DE DE_OUT DE_OUT DE_OUT OSD_VS VS_OUT VS_OUT VS_OUT OSD_HS HS_OUT HS_OUT HS_OUT OSD_CLK CLK_OUT CLK_OUT CLK_OUT OSD_IN.23 OSD_IN.23 OSD_IN.21 OSD_IN.20... - Page 426 ADV8003 Hardware Manual P.34 P.33 P.32 P.31 P.30 P.29 P.28 P.27 P.26 P.25 P.24 P.23 P.22 P.21 P.20 P.19 P.18 P.17 P.16 P.15 P.14 P.13 P.12 P.11 P.10 Rev. B, August 2013...
- Page 427 ADV8003 Hardware Manual Rev. B, August 2013...
-
Page 428: Table 99: Ycrcb Ttl Output Formats
ADV8003 Hardware Manual Table 99: YCrCb TTL Output Formats ADV8003 PIN 16-BIT SDR 4:2:2 20-BIT SDR 4:2:2 24-BIT SDR 4:2:2 24-BIT SDR 4:4:4 30-BIT SDR 4:4:4 36-BIT SDR 4:4:4 NAME YCbCr Colorspace OSD_DE DE_OUT DE_OUT DE_OUT DE_OUT DE_OUT DE_OUT OSD_VS... - Page 429 ADV8003 Hardware Manual P.35 Cb11 P.34 Cb10 P.33 P.32 P.31 P.30 P.29 P.28 P.27 P.26 P.25 P.24 P.23 P.22 P.21 P.20 P.19 P.18 P.17 P.16 P.15 P.14 P.13 P.12 P.11 P.10 Rev. B, August 2013...
- Page 430 ADV8003 Hardware Manual VID_DE VID_HS VID_VS VID_CLK Rev. B, August 2013...
-
Page 431: List Of Figures
Figure 43: DDR2 Loopback Test Architecture ................................117 Figure 44: VBI Data Extraction Block Diagram ................................. 120 Figure 45: ADV8003 Image Processing Colorimetry Breakdown ........................... 125 Figure 46: 720(1440) x 240p @ 59.94/60Hz, CEA Formats 8 and 9 ......................... 130 Figure 47: Primary Input Channel CSC .................................. - Page 432 Figure 77: Data Loaded from SPI Flash Through ADV8003 SPI Master Interface ....................218 Figure 78: MCU as SPI Master Sending OSD Data Through ADV8003 SPI Slave Interface ................219 Figure 79: SPI Loopback Enabled so MCU Can Program SPI Flash ........................220 Figure 80: SPI Slave Interface Timing and Data Format ............................
- Page 433 ADV8003 Hardware Manual Figure 105: Simplified View of ADV8003 Encoder Block............................308 Figure 106: SD Luma SSAF Filter, Programmable Responses ..........................316 Figure 107: SD Luma SSAF Filter, Programmable Gains ............................317 Figure 108: SD Luma SSAF Filter, Programmable Attenuation ..........................317 Figure 109: PrPb SSAF Filter ......................................
- Page 434 ADV8003 Hardware Manual Figure 158: ADV8003 Schematic – Page 18 ................................380 Figure 159: ADV8003 Schematic – Page 19 ................................381 Figure 160: ADV8003 Schematic – Page 20 ................................382 Figure 161: ADV8003 Schematic – Page 21 ................................383 Figure 162: ADV8003 Schematic – Page 22 ................................383 Figure 163: ADV8003 Schematic –...
-
Page 435: List Of Tables
Table 9: Frame Tracking ......................................... 113 Table 10: Indication of ADV8003 Capabilities with One DDR2 Memory......................115 Table 11: Indication of ADV8003 Capabilities with Two DDR2 Memories ......................116 Table 12: Indication of ADV8003 Capabilities with Different Memory Sizes ......................116 Table 13: Output Mode Outline .................................... - Page 436 Table 64: Recommended N and Expected CTS Values for 48 kHz and Multiples ....................275 Table 65: I S Channel Status ADV8003 Register Map Location of Fixed Value ..................... 278 Table 66: Audio InfoFrame Configuration Registers ..............................280 Table 67: ACP Packet Configuration Registers ................................281 Table 68: ISRC1 Packet Configuration Registers ...............................
-
Page 437: List Of Equations
ADV8003 Hardware Manual LIST OF EQUATIONS Equation 1: Calculating DPLL Phase Period ................................110 Equation 2: Calculating DPLL Clock Period ................................110 Equation 3: DDR2 Memory Interface Clock Frequency ............................115 Equation 4: Primary Input CSC Channel A Output ..............................131 Equation 5: Primary Input CSC Channel B Output .............................. -
Page 438: Revision History
1.1. OVERVIEW updated 1.1.1. Digital Video Input updated Updated functional block diagram R_TX1 and R_TX2 resistors updated in pin list 2. ADV8003 TOP LEVEL CONTROL updated Figure 11: ADV8003 Simplified Block Diagram updated 2.1.1. Selecting a Mode updated Rev. B, August 2013... - Page 439 2.2.4. Clock Configuration updated 2.2.5.1. DDR2 Configuration updated Table 7: Indication of ADV8003 Capabilities with 2 DDR2 Memories updated Table 8: Indication of ADV8003 Capabilities with 1 DDR2 Memory updated 2.2.8. VBI Data Insertion updated Figure 36: ADV8003 Image Processing Colorimetry Breakdown updated 2.2.11.
- Page 440 ADV8003 Hardware Manual 8.2. INPUT CONFIGURATION updated Figure 91: Simplified View of ADV8003 Encoder Block updated 8.4.6. SD Noninterlaced Mode (240p/288p) updated 8.4.9. Color Space Conversion Matrix updated 9.2. RX SECTION updated 9.3. VSP AND OSD SECTION updated 9.4. TX CORE updated...
Need help?
Do you have a question about the ADV8003 and is the answer not in the manual?
Questions and answers