Figure 90: Aes3 Stream Format Input To Adv8003; Figure 91: Timing Of Standard I2S Stream Input To Adv8003; Figure 92: Timing For Right-Justified I2S Stream Input To Adv8003; Figure 93: Timing For Left-Justified I2S Stream Input To Adv8003 - Analog Devices ADV8003 Hardware Manual

L
S
B
LRCLK
SCLK
DATA
LRCLK
SCLK
DATA
LRCLK
SCLK
DATA
Rev. B, August 2013
Data
31
0

Figure 90: AES3 Stream Format Input to ADV8003

LEFT
MSB
32 Clock Slots

Figure 91: Timing of Standard I2S Stream Input to ADV8003

LEFT
MSB MSB MSB
MSB
MSB extended
32 Clock Slots

Figure 92: Timing for Right-Justified I2S Stream Input to ADV8003

LEFT
MSB
32 Clock Slots

Figure 93: Timing for Left-Justified I2S Stream Input to ADV8003

23 24
M
S V
B
Validity Flag
User Data
Channel Status
Block Start Flag
RIGHT
LSB MSB
RIGHT
LSB MSB
MSB-1
MSB extended
RIGHT
LSB MSB
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ADV8003 Hardware Manual
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U C B 0 0
LSB
32 Clock Slots
MSB MSB MSB
MSB-1
32 Clock Slots
LSB
32 Clock Slots
31
0 0
LSB