2.1.7.
Mode 6
Mode 6 should be used if:
•
Two separate upscaled resolutions are required
•
De-interlacing is not required
•
OSD is required on one resolution only (preferably the lower upscaled resolution output)
Input
Input
Exosd
Exosd
720p OSD
720p OSD
Muxing
Muxing
24-bit
24-bit
from
from
Input
Input
External FPGA
External FPGA
Port
Port
Video
Video
480p Video
480p Video
36-bit
36-bit
from
from
Input
Input
Decoder
Decoder
Port
Port
Serial
Serial
Video
Video
RX
RX
Mode 6 places the OSD blend block after the SVSP. Both the PVSP block and SVSP work in parallel in this mode. As the OSD is only on
one data path, it will only be displayed at a single resolution. As shown in the example in
progressive format. Therefore, this mode can only be used when the input is progressive.
It can be seen from
Figure 20
OSD blend block, the OSD can only be generated on a single output resolution.
Note: De-interlaced inputs can be input to the device in this mode. However, the SVSP can only accept progressive input formats.
Therefore, the SVSP would be excluded from the processing in this case as would the OSD blend.
Rev. B, August 2013
Mode 6
Mode 6
DDR2 Memory
DDR2 Memory
Interface
Interface
Build
Build
Scale
Scale
(720p)
(720p)
OSD
OSD
OSD
OSD
(720p)
(720p)
Video
Video
Muxing
Muxing
Secondary:
Secondary:
Data
Data
Formatting
Formatting
& CSC
& CSC
Primary:
Primary:
Data
Data
(480p)
(480p)
Formatting,
Formatting,
CSC & ACE
CSC & ACE
RX:
RX:
Data
Data
Formatting
Formatting
& CSC
& CSC
Figure 20: ADV8003 Mode 6 Configuration
that the same output formats can be generated in this mode. However, due to the change in location of the
(720p)
(720p)
Primary
Primary
VSP
VSP
(1080p)
(1080p)
Secondary
Secondary
OSD
OSD
VSP
VSP
Blend
Blend
(720p)
(720p)
(720p)
(720p)
77
ADV8003 Hardware Manual
Output
Output
Muxing
Muxing
Figure
20, the input to the SVSP must be a
HDMI
HDMI
Tx1
Tx1
1080p
1080p
HDMI
HDMI
Tx2
Tx2
1080p
1080p
HD
HD
Encoder
Encoder
720p(OSD)
720p(OSD)
SD
SD
Encoder
Encoder
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