Analog Devices ADV8003 Hardware Manual page 175

Function
pvsp_dp_activeline[11:
0]
0x000 
0xXXX
pvsp_dp_vfrontporch[9:0], Primary VSP Map, Address 0xE860[1:0]; Address 0xE861[7:0]
This signal is used to set the vertical front porch duration of output timing. This register's value will be used while
pvsp_autocfg_output_vid is 0.
Function
pvsp_dp_vfrontporch[9
:0]
0x000 
0xXXX
pvsp_dp_vsynctime[9:0], Primary VSP Map, Address 0xE862[1:0]; Address 0xE863[7:0]
This signal is used to set the vertical synchronous time duration of output timing. This register's value will be used while
pvsp_autocfg_output_vid is 0.
Function
pvsp_dp_vsynctime[9:0
]
0x000 
0xXXX
pvsp_dp_vbackporch[9:0], Primary VSP Map, Address 0xE864[1:0]; Address 0xE865[7:0]
This signal is used to set the vertical back porch duration of output timing. This register's value will be used while
pvsp_autocfg_output_vid is 0.
Function
pvsp_dp_vbackporch[9:
0]
0x000 
0xXXX
pvsp_dp_vpolarity, Primary VSP Map, Address 0xE869[0]
This bit is used to set the polarity of output VSync. This register's value will be used while pvsp_autocfg_output_vid is 0.
Function
pvsp_dp_vpolarity
0 
1
pvsp_dp_hpolarity, Primary VSP Map, Address 0xE869[1]
This bit is used to set the polarity of output HSync. This register's value will be used while pvsp_autocfg_output_vid is 0.
Rev. B, August 2013
Description
Default
Active lines of output timing
Description
Default
Vertical front porch of output timing
Description
Default
VSync width of output timing
Description
Default
Vertical back porch of output timing
Description
Low
High
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ADV8003 Hardware Manual