Figure 134: Level And Edge-Sensitive Raw, Status And Interrupt Generation - Analog Devices ADV8003 Hardware Manual

edge_sensitive_int_raw, IO, Address 0xXX (Read Only)
This readback indicates the status of the edge sensitive interrupt. When set to 1, it indicates that an event has occured. Once set, this bit
remains high until the interrupt is cleared via edge_sensitive_int_clr.
Function
edge_sensitive_int_raw
0 
1
Level-senstivitive bit, level_sensitive_int_raw, always represents the current status of whether or not a particular event or condition is
occurring e.g. if the part is receiving AVI InfoFrames. It is not a latched bit and never requires to be cleared.
Edge-sensitive bit, edge_sensitive_int_raw, indicates that a transient event or condition has occurred; it is latched and it needs to be
cleared. This approach is adopted for important events which have a transient nature e.g. if the part has received a new AVI Infoframe. If
edge_sensitive_int_raw did not latch and returned to 0 some time after the event occurred, the user could miss the fact that the event or
condition occurred. Therefore, edge-sensitive raw bits do not truly represent the current status; instead, the represent the status of an edge
event that happened in the past. To clear a latched bit, the user must set the corresponding clear bit to 1.
Figure 134, Figure 135 and
xxx_RAW
Internal
Status Flag
Internal
Pulse Flag
Rev. B, August 2013
Description
No event/condition occured
Event/condition occured
Figure 136 provide a graphical example of what how edge and level sensitive interrups operate.
CHANGE
DETECTION
SAMPLING
(Rising and
Falling edge)
CHANGE
SAMPLING DETECTION
(Rising edge)

Figure 134: Level and Edge-sensitive Raw, Status and Interrupt Generation

xxx_ST
HOLD UNTIL APPLY
CLEARED MASK
xxx_CLR xxx_MB1
yyy_CLR yyy_MB1
HOLD UNTIL APPLY
CLEARED MASK
yyy_RAW yyy_ST
351
ADV8003 Hardware Manual
Interrupt path for level
sensitive Interrupts
INT
OR
Output
Interrupt path for edge
sensitive Interrupts