Output Configuration; Table 76: Standards Directly Supported By Adv8003 Encoder Processor - Analog Devices ADV8003 Hardware Manual

I = interlaced, P = progressive.

8.3. OUTPUT CONFIGURATION

Once the input to the encoder section has been configured, the user can configure the output of the encoder DACs. Depending on the
input mode specified by the
dac6_sel[2:0].
It is important to note that if the
of YPbPr or RGB, and DACs 4-6 can only output the SD signals of CVBS or black burst or luma or chroma. It is possible to multiplex any
of the ED/HD signals out on any of the DACs 1 to 3 in simultaneous mode. Similarly, it is possible to multiplex any of the SD signals out
on any of the DACs 4 to 6.
dac1_sel[2:0], Encoder Map, Address 0xE42A[2:0]
This signal selects the data that is supplied to DAC 1.
Rev. B, August 2013

Table 76: Standards Directly Supported by ADV8003 Encoder Processor

Active I/P
Resolution
720 × 240 P
720 × 288 P
720 × 480 I
720 × 576 I
720 × 483 P
720 × 483 P
720 × 483 P
720 × 576 P
720 × 483 P
720 × 576 P
1920 × 1035 I
1920 × 1035 I
1280 × 720 P
1280 × 720 P
1920 × 1080 I
1920 × 1080 I
1920 × 1080 I
1920 × 1080 I
1920 × 1080 P
1920 × 1080 P
1920 × 1080 P
1920 × 1080 P
1920 × 1080 P
func_mode[2:0] register, the DAC outputs can be configured accordingly using
func_mode[2:0] signal is set to simultaneous mode; then DACs 1-3 can only output the ED/HD signals
Frame Standard
Rate (Hz)
59.94
50
29.97 ITU-R BT.601/656
25 ITU-R BT.601/656
59.94 SMPTE 293M
59.94 BTA T-1004
59.94 ITU-R BT.1358
50 ITU-R BT.1358
59.94 ITU-R BT.1362
50 ITU-R BT.1362
30 SMPTE 240M
29.97 SMPTE 240M
60, 50, 30, SMPTE 296M
25, 24
23.97, SMPTE 296M
59.94,
29.97
30, 25 SMPTE 274M
29.97 SMPTE 274M
25 SMPTE 295
50 ITU-R BT.709-5
30, 25, 24 SMPTE 274M
23.98, SMPTE 274M
29.97
24 ITU-R BT.709-5
50 SMPTE 295
50, 59.94, SMPTE 274M
60
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ADV8003 Hardware Manual
dac1_sel[2:0] to