Figure 34: Ddr Mode, Luma And Chroma Swap - Analog Devices ADV8003 Hardware Manual

Function
vid_format_sel[4:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08 
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
vid_swap_bus_ctrl[2:0], IO Map, Address 0x1B48[7:5]
This signal is used to control the video input pixel bus. The input pixel bus is 36 bits wide and is divided into three data channels: Top =
D[35:24], Middle = D[23:12] and Bottom = D[11:0]. This register allows the user to swap the order of these three data channels.
Function
vid_swap_bus_ctrl[2:0]
000 
001
010
011
100
101
110
111
The input formatter also has a number of controls which can be used to provide extra flexibility in terms of data processing.
Once a DDR mode is selected using vid_format_sel[4:0], the order of the luma and chroma data can be configured using
vid_ddr_yc_swap. In DDR modes, the luma is expected on the rising edge of the pixel clock. Setting this bit to 1 swaps the luma and
chroma samples and places the chroma sample (C) on the rising edge and the luma sample (Y) on the falling edge. Refer to
more information. The edge on which each sample of DDR data is latched into the part can be specified using vid_ddr_edge_sel.
Rev. B, August 2013
Description
1 x 8-bit bus, SDR 4:2:2
1 x 10-bit bus, SDR 4:2:2
1 x 12-bit bus, SDR 4:2:2
2 x 8-bit buses, SDR 4:2:2
2 x 10-bit buses, SDR 4:2:2
2 x 12-bit buses, SDR 4:2:2
3 x 8-bit buses, SDR 4:4:4 (P[35:28], P[23:16], P[11:4])
3 x 10-bit buses, SDR 4:4:4 (P[35:26], P[23:14], P[11:2])
3 x 12-bit buses, SDR 4:4:4
1 x 8-bit bus, DDR 4:2:2
1 x 10-bit bus DDR 4:2:2
1 x 12 bit bus, DDR 4:2:2
3 x 8 bit buses, SDR 4:4:4 (P[23:0])
2 x 3 x 8-bit interleaved buses, SDR 4:4:4
2 x 2 x 8-bit interleaved buses, SDR 4:2:2
2 x 2 x 10-bit interleaved buses, SDR 4:2:2
2 x 2 x 12-bit interleaved buses, SDR 4:2:2
3 x 10-bit buses, SDR 4:4:4 (P[29:0])
3 x 7-bit buses, SDR 4:4:4 (for external alpha blend)
3 x 10-bit buses, SDR 4:4:4 (OSD_IN[23:0] and P[35:30])
Description
D[35:24] D[23:12] D[11:0]
D[35:24] D[11:0] D[23:12]
D[35:24] D[23:12] D[11:0]
D[23:12] D[35:24] D[11:0]
D[11:0] D[35:24] D[23:12]
D[11:0] D[23:12] D[35:24]
D[23:12] D[11:0] D[35:24]
D[35:24] D[23:12] D[11:0]
Y Y C C Y Y C C Y Y
C C Y Y C C Y Y C C

Figure 34: DDR Mode, Luma and Chroma Swap

C C Y Y C C ddr_yc_swap = 0 ddr_yc_swap = 0
Y Y C C Y Y ddr_yc_swap = 1 ddr_yc_swap = 1
94
ADV8003 Hardware Manual
Figure 34 for