Serial Video Receiver; Detect; Figure 82: Functional Block Diagram Of Adv8003 Serial Video Rx - Analog Devices ADV8003 Hardware Manual

5. SERIAL VIDEO RECEIVER

The Serial Video Rx on the ADV8003KBCZ-8x derivatives can receive video data at rates of up to 3 GHz. This allows support for video
formats ranging from SD to 4k x 2k @ 24Hz, 1080p120Hz and 1080p60 3D. The Serial Video Rx on the ADV8003KBCZ-7x derivatives
can receive video data at rates of up to 2.25 GHz. This allows support for video formats ranging from SD to 1080p @ 60Hz 12-bit. It is
designed for chip-to-chip connection only and, as such, does not offer any DDC lines to facilitate HDCP or EDID operations.
RX_C±
RX_0±
RX_1±
RX_2±
This section outlines the various registers available to the user in the register map which is used to control the Serial Video Rx. These
registers are used to configure the ADV8003 to accept input video from a device such as an HDMI transceiver (for example, ADV7623) or
a front end device with HDMI output (for example, ADV7850).
5.1. + 5 V DETECT
The Serial Video Rx on the ADV8003 can monitor the level on the +5 V power signal pin. This +5 V signal can be used to reset the Rx
section if requested. If +5 V detection is not being used, this pin should be connected to a +5 V supply. The controls for +5 V detection
can be found in the following I
filt_5v_det_dis, HDMI RX Map, Address 0xE256[7]
This bit is a control to disable the digital glitch filter on the HDMI 5V detect signals. The filtered signals are used as interrupt flags, and
also used to reset the HDMI section. The filter works from an internal ring oscillator clock and is therefore available in power-down
mode. The clock frequency of the ring oscillator is 42MHz +/-10%.
Note: If the 5 V pins are not used and left unconnected, the 5 V detect circuitry should be disconnected from the HDMI reset signal by
setting DIS_CABLE_DET_RST to 1. This avoids holding the HDMI section in reset.
Function
filt_5v_det_dis
0 
1
Note: If the +5 V pins are not used and left unconnected, the +5 V detect circuitry should be disconnected from the Rx reset circuitry by
setting dis_cable_det_rst to 1. This avoids holding the Rx section in reset.
filt_5v_det_timer[6:0], HDMI RX Map, Address 0xE256[6:0]
This bit is a control to set the timer for the digital glitch filter on the HDMI +5 V detect inputs. The unit of this parameter is 2 clock
cycles of the ring oscillator (~ 47ns). The input must be constantly high for the duration of the timer, otherwise the filter output remains
low. The output of the filter returns low as soon as any change in the +5 V power signal is detected.
Rev. B, August 2013
PLL
Sampler

Figure 82: Functional Block Diagram of ADV8003 Serial Video Rx

C registers. These registers are valid even when the part is not processing TMDS information.
2
Description
Enabled
Disabled
Deep Colour
Conversion
Packet
Processor
227
ADV8003 Hardware Manual
To ADV8003
Digital Core
Packet/
Infoframe
Memory