Interrupt Architecture Overview; Table 90: Serial Video Rx Level Sensitive Interrupts; Table 91: Serial Video Rx Edge Sensitive Interrupts - Analog Devices ADV8003 Hardware Manual

Function
edge_sensitive_int_mb2
0 
1
In this section, all raw bits are classified as being triggered by either level-sensitive or edge-sensitive events, with the following
understanding of the terminology.
Level-sensitive events are events that are generally either high or low and which are not expected to change rapidly. The raw bit for level-
sensitive events is not latched and, therefore, always represents the true real-time status of the event in question.
Edge-sensitive events are events that only exist for an instant. The raw bits for edge-sensitive events are latched and, therefore, represent
the occurrence of an edge-sensitive event that happened in the past. Raw bits for edge-sensitive events must be cleared by the
corresponding clear bit.
9.2.2.

Interrupt Architecture Overview

The following is a complete list of Serial Video Rx interrupts, their mode of operation (edge or level sensitive) and a description of each
interrupt.
Interrupt
rx_cable_det_raw/st/mb1/clr
rx_tmdspll_lck_raw/st/mbx/clr
rx_tmds_clk_det_raw/st/mbx/clr
rx_video_3d_raw/st/mbx/clr
rx_av_mute_raw/st/mbx/clr
rx_hdmi_mode_raw/st/mbx/clr
rx_gen_ctl_pckt_raw/st/mbx/clr
rx_gamut_mdata_
pckt_raw/st/mbx/clr
rx_isrc2_pckt_raw/st/mbx/clr
rx_isrc1_pckt_raw/st/mbx/clr
rx_vs_info_frm_raw/st/mbx/clr
rx_ms_info_frm_raw/st/mbx/clr
rx_spd_info_frm_ raw/st/mbx/clr
rx_avi_info_frm_raw/st/mbx/clr
Interrupt
rx_vs_inf_cks_err_
edge_raw/st/mb2/clr
rx_ms_inf_cks_err
_edge_ raw/st/mb2/clr
rx_spd_inf_cks_er
r_edge_raw/st/mb2/clr
rx_avi_inf_cks_err
_edge_raw/st/mb2/clr
rx_deepcolor_chn
g_edge_raw/st/mb2/clr
rx_tmds_clk_chng
_edge_raw/st/mb2/clr
rx_pkt_err_edge_ raw/st/mb2/clr
Rev. B, August 2013
Description
Disable edge_sensitive_int detection interrupt for INT2
Enable edge_sensitive_int detection interrupt for INT2

Table 90: Serial Video Rx Level Sensitive Interrupts

Mode of Operation
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive

Table 91: Serial Video Rx Edge Sensitive Interrupts

Mode of Operation
Edge sensitive
Edge sensitive
Edge sensitive
Edge sensitive
Edge sensitive
Edge sensitive
Edge sensitive
Description
Used to detect if the Serial Video inputs are connected to an upstream IC
Used to indicate if the TMDS PLL has locked to the incoming TMDS clock
Used to indicate activity on the TMDS clock line
Used to indicate if the incoming video is 3D format
Used to indicate the AVMUTE value from the general control packet
Used to indicate if the incoming video is HDMI mode or DVI mode
Used to indicate if a general control packet has been detected
Used to indicate if a gamut metadata packet has been detected
Used to indicate if an ISRC2 packet has been detected
Used to indicate if an ISRC1 packet has been detected
Used to indicate if a vendor specific InfoFrame has been detected
Used to indicate if an MPEG source InfoFrame has been detected
Used to indicate if an SPD InfoFrame has been detected
Used to indicate if an AVI InfoFrame has been detected
Description
Used to indicate if there was an error with the vendor specific InfoFrame
Used to indicate if there was an error with the MPEG source InfoFrame
Used to indicate if there was an error with a SPD InfoFrame
Used to indicate if there was an error with the AVI InfoFrame
Used to indicate if the incoming video is deep color. The exact mode
can be determined by reading the DEEP_COLOR_MODE register
Used to indicate if the incoming TMDS clock has changed frequency
Used to indicate if there was an error with any HDMI packet
354
ADV8003 Hardware Manual