Analog Devices ADV8003 Hardware Manual page 103

the polarity of the upstream IC. If active low, these register can be left at their default. If these signals from the upstream IC are active
high, their polarity can be inverted.
exosd_hs_pol, IO Map, Address 0x1B69[0]
This bit is used to set the polarity of the input External OSD HS timing signal.
Function
exosd_hs_pol
0 
1
exosd_vs_pol, IO Map, Address 0x1B69[1]
This bit is used to set the polarity of the input External OSD VS timing signal.
Function
exosd_vs_pol
0 
1
exosd_de_pol, IO Map, Address 0x1B69[2]
This bit is used to set the polarity of the input External OSD DE timing signal.
Function
exosd_de_pol
0 
1
exosd_hs_vs_mode is used to select the method by which the input video will be synchronized. This may be required when the ADV8003
is used in conjunction with an MPEG decoder. MPEG decoders use embedded timing codes rather than using external HS and VS signals.
Similarly, other ADI decoders/HDMI Rxs can output video using embedded timing codes. This register should be programmed
depending on the timing method of the upstream IC.
Refer to Section 2.2.11 for more information on AV-codes.
exosd_hs_vs_mode, IO Map, Address 0x1B6B[7]
This bit is used to select the method of input timing.
Function
exosd_hs_vs_mode
0
1 
exosd_av_pos_sel, IO Map, Address 0x1B6B[3]
This bit is used to select if the HS generated is consistent with EIA 861 timing or dependant on the embedded timing codes.
Rev. B, August 2013
Description
Input HS polarity doesn't change.
Input HS polarity gets inverted.
Description
Input VS polarity doesn't change.
Input VS polarity gets inverted.
Description
Input DE polarity doesn't change.
Input DE polarity gets inverted.
Description
Embedded timing codes
VS/DE mode
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ADV8003 Hardware Manual