Programmable Dac Gain Control; Figure 113: Programmable Dac Gain - Positive And Negative Gain - Analog Devices ADV8003 Hardware Manual

Double buffering can be activated on the following SD functions: the SD gamma A and gamma B curves, SD Y scale, SD Cr scale, SD Cb
scale, SD brightness, SD closed captioning, and SD Macrovision bits (Reg 0xE4E0, Bits [5:0]).

8.4.16. Programmable DAC Gain Control

It is possible to adjust the DAC output signal gain up or down from its absolute level. This is illustrated in
In Case A of Figure 113, the video output signal is gained. The absolute level of the sync tip and the blanking level increase with respect to
the reference video output signal. The overall gain of the signal is increased from the reference signal.
In Case B of Figure 113, the video output signal is reduced. The absolute level of the sync tip and the blanking level decrease with respect
to the reference video output signal. The overall gain of the signal is reduced from the reference signal.
The range of this feature is specified for ±7.5% of the nominal output from the DACs. For example, if the output current of the DAC is
4.33 mA, the DAC gain control feature can change this output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%). To enable the gain
for the relevant set of DACs,
dac4to6_tuning[7:0], Encoder Map, Address 0xE40A[7:0]
This register is used to set the gain for DACs 4-6 output voltage.
Rev. B, August 2013
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0x0A, 0x0B
700mV
300mV
CASE B
700mV
300mV
Figure 113: Programmable DAC Gain – Positive and Negative Gain
dac4to6_tuning[7:0] and dac1to3_tuning[7:0]
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0x0A, 0x0B
must be configured.
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ADV8003 Hardware Manual
Figure 113.