Pcb Layout Recommendations; Analogue/Digital Video Interface Outputs; External Ddr2 Memory Requirements; Appendix A - Analog Devices ADV8003 Hardware Manual

APPENDIX A

PCB LAYOUT RECOMMENDATIONS

The ADV8003 is a high precision, high speed, mixed signal device. It is important to have a well laid out PCB board in order to achieve
the maximum performance from the part. The following sections are a guide for designing a board using the ADV8003.

Analogue/Digital Video Interface Outputs

The HDMI TMDS trace pairs must have a 100Ω differential impedance and should be routed in the shortest trace length possible to
minimize the possibility of cross talk with other signals. The HDMI TMDS trace pairs must be routed on the same side of the PCB as the
ADV8003 and should not be routed through vias to any other layers. A solid plane must be maintained underneath the HDMI TMDS
trace pairs for their full trace length. Any external ESD suppressors should be placed as close as possible to the HDMI connector to reduce
the impact on impedance TDR measurements.
If the ADV8003KBCZ-8/8B/8C device is to support 3 GHz signals from the HDMI Txs, it is recommended the TMDS trace widths are set
to 0.2 mm. The spacing of the traces, the height of the copper and the trace's height above the ground plan should all be controlled to
maintain the trace impedance with this trace width.
The encoder analog outputs must have a 75Ω characteristic impedance and should be routed in the shortest trace length possible to
minimize the possibility of cross talk with other signals. To assist in reducing cross talk, ground traces can be added between adjacent
encoder analog outputs. The encoder analog outputs must be routed on the same side of the PCB as the ADV8003 and should not be
routed through vias to any other layers. A solid plane must be maintained underneath the encoder analog outputs for their full trace
length. The termination resistors on the encoder analog outputs should be kept as close as possible to the ADV8003. Any external filtering
on the encoder outputs should be placed as close as possible to the analog connectors.

External DDR2 Memory Requirements

The ADV8003 must be placed as close to and on the same side of the PCB as the external DDR2 memories. Balanced T-routing should be
used for all shared connections between the ADV8003 and the external DDR2 memories. All traces should be 75Ω and impedance
controlled to ensure robust timing. Traces should be routed on the same side of the PCB as the devices where possible. If this is not
possible, all traces should be kept on the outer layers.
All differential signals (for example, DDR_CK and DDR_CKB) should be treated as described above. These signals should be routed in
parallel and on the same side of the PCB. Match the DDR_CK trace length to DDR_CKB trace length to 20 mils (0.5 mm). Any stubs on
the clock lines should be kept as short as possible to avoid signal reflections.
The following 4-byte wide data lanes should be matched to within 50 mils on the PCB layout. The precise matching of these signals is
critical.
• DDR3_DM3, DDR_DQS3, DDR_DQSB3, DDR_DQ31 – DDR_DQ24
• DDR2_DM2, DDR_DQS2, DDR_DQSB2, DDR_DQ23 – DDR_DQ16
• DDR1_DM1, DDR_DQS1, DDR_DQSB1, DDR_DQ15 – DDR_DQ8
• DDR0_DM0, DDR_DQS0, DDR_DQSB0, DDR_DQ7 – DDR_DQ0
Different byte lanes are to be matched to 200 mils (5.08 mm) of each other. 47Ω series termination resistors should be placed as close to
the source (ADV8003) as possible on the following signals:
• Address signals – DDR_A12-DDR_A0 and DDR_BA0-DDR_BA2
• Clock differential signals – DDR_CK and DDR_CKB (use discrete resistors for these two signals)
• Control signal – DDR_CKE and command signals – DDR_CSB, DDR_RASB, DDR_CASB, and DDR_WEB
• Data mask signals – DDR_DM3-DDR_DM0
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ADV8003 Hardware Manual