Spi Master Interface; Figure 81: Spi Master Interface Timing And Data Format - Analog Devices ADV8003 Hardware Manual

Function
spi_filter_sel
0 
1

4.2.8.3. SPI Master Interface

The ADV8003 SPI master interface (serial port 2) is used by the ADV8003 to read the OSD binary file (output by Blimp OSD) from an
external SPI flash memory, and to copy it to the DDR2 memory. Note that the library of functions provided by ADI will take care of this
process; the information in this section is just provided so the user can find a suitable SPI flash memory which can be interfaced to the
ADV8003 SPI master interface.
The SPI master is designed to be compatible with the M25P16 and supports the FAST_READ command. The SPI master clock can be
configured to support up to 80 MHz. The SPI master, similar to the slave, can support the following modes:
• CPOL = 0, CPHA=0
• CPOL = 0, CPHA=1
• CPOL = 1, CPHA=0
• CPOL = 1, CPHA=1
Figure 81 shows the effect that these settings may have on the data.
CS2
CPOL CPHA
SCK2
0 0
SCK2
0 1
SCK2
1
0
SCK2
1
1
MOSI2
MISO2
The CPOL/CPHA can be configured through the following I
spi_master_cpol, IO Map, Address 0x1A14[1]
This bit is used to select the SPI master clock polarity.
Function
spi_master_cpol
0 
1
spi_master_cpha, IO Map, Address 0x1A14[0]
This bit is used to select the SPI master clock phase.
Rev. B, August 2013
Description
2ns glitch rejection
5ns glitch rejection
Instruction(0x0B)
24-bit Address
23 22 21 ... 3

Figure 81: SPI Master Interface Timing and Data Format

Description
Idle state, clock is low
Idle state, clock is high
Dummy Byte
2 1 0 7 6 5 4 3 2 1 0
C registers.
2
225
ADV8003 Hardware Manual
Data out 1 Data out 2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0