Packet Registers; Isrc Packet Registers; Table 42: Isrc1 Packet Registers - Analog Devices ADV8003 Hardware Manual

Video signal processor with motion adaptive deinterlacing, scaling, bitmap osd, dual hdmi tx and video encoder
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InfoFrame
Map Address
0xE35F
0xE360
0xE361
0xE362
0xE363
0xE364
0xE365
0xE366
0xE367
0xE368
0xE369
0xE36A
0xE36B
0xE36C
0xE36D
0xE36E
0xE36F
The Vendor Specific InfoFrame registers are considered valid if the following two conditions are met:
vs_infoframe_det is 1.
vs_inf_cksum_err is 0. This condition applies only if

5.10. PACKET REGISTERS

5.10.1. ISRC Packet Registers

Table 42
and
Table 43
provide lists of the readback registers available for the ISRC packets. Refer to the HDMI 1.4 specifications for a
detailed explanation of the ISRC packet fields.
Rev. B, August 2013
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

Table 42: ISRC1 Packet Registers

InfoFrame
R/W
Map Address
0xF2
R/W
0xF3
R
0xF4
R
0x8C
R
0x8D
R
0x8E
R
0x8F
R
0x90
R
0x91
R
0x92
R
0x93
R
0x94
R
0x95
R
0x96
R
0x97
R
0x98
R
0x99
R
0x9A
R
Register Name
vs_inf_pb_0_12
vs_inf_pb_0_13
vs_inf_pb_0_14
vs_inf_pb_0_15
vs_inf_pb_0_16
vs_inf_pb_0_17
vs_inf_pb_0_18
vs_inf_pb_0_19
vs_inf_pb_0_20
vs_inf_pb_0_21
vs_inf_pb_0_22
vs_inf_pb_0_23
vs_inf_pb_0_24
vs_inf_pb_0_25
vs_inf_pb_0_26
vs_inf_pb_0_27
vs_inf_pb_0_28
always_store_inf
is set to 1.
Register Name
isrc1_packet_id[7:0]
isrc1_header1
isrc1_header2
isrc1_pb_0_1
isrc1_pb_0_2
isrc1_pb_0_3
isrc1_pb_0_4
isrc1_pb_0_5
isrc1_pb_0_6
isrc1_pb_0_7
isrc1_pb_0_8
isrc1_pb_0_9
isrc1_pb_0_10
isrc1_pb_0_11
isrc1_pb_0_12
isrc1_pb_0_13
isrc1_pb_0_14
isrc1_pb_0_15
239
ADV8003 Hardware Manual
Byte Name
Data Byte 11
Data Byte 12
Data Byte 13
Data Byte 14
Data Byte 15
Data Byte 16
Data Byte 17
Data Byte 18
Data Byte 19
Data Byte 20
Data Byte 21
Data Byte 22
Data Byte 23
Data Byte 24
Data Byte 25
Data Byte 26
Data Byte 27
Packet Byte No.
1
Packet Type Value
HB1
HB2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14

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