Figure 83: Hdmi Video Fifo - Analog Devices ADV8003 Hardware Manual

T M D S
C l o c k
T M D S
C h a n n e l 0
T M D S
C h a n n e l 1
T M D S
C h a n n e l 2
The video FIFO is designed to operate completely autonomously. It automatically resynchronizes the read and write pointers if they are
about to point to the same location. However, it is also possible for the user to observe and control the FIFO operation with a number of
FIFO control and status registers described below.
dcfifo_level[2:0], HDMI RX Map, Address 0xE21C[2:0] (Read Only)
This signal is a readback to indicate the distance between the read and write pointers. Overflow and underflow will read as level 0. The
ideal centered functionality will read as 0b100.
Function
dcfifo_level[2:0]
000 
001
010
011
100
101
110
111
dcfifo_locked, HDMI RX Map, Address 0xE21C[3] (Read Only)
This bit is a readback to indicate if the Video FIFO is locked.
Function
dcfifo_locked
0 
1
dcfifo_recenter, HDMI RX Map, Address 0xE25A[2] (Self-Clearing)
This bit is used as a reset to recenter the Video FIFO. This is a self clearing bit.
Function
dcfifo_recenter
0 
1
Rev. B, August 2013
T M D S
+
-
P L L
T M D S C h 0
+
-
T M D S
S a m p l i n g
T M D S C h 1
+
a n d
-
D a t a
R e c o v e r y
T M D S C h 2
+
-

Figure 83: HDMI Video FIFO

Description
FIFO has underflowed or overflowed
FIFO is about to overflow
FIFO has some margin
FIFO has some margin
FIFO perfectly balanced
FIFO has some margin
FIFO has some margin
FIFO is about to underflow
Description
Video FIFO is not locked. Video FIFO had to resynchronize between previous two VSyncs
Video FIFO is locked. Video FIFO did not have to resynchronize between previous two VSyncs
Description
Video FIFO normal operation
Video FIFO to re-centre
D i v i d e r
R
1 2
G
1 0
1 2
T M D S
B
D e c o d i n g
1 0
1 2
H S
V S
1 0
D E
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ADV8003 Hardware Manual
D P L L
R
1 2
G
1 2
B
F I F O
1 2
H S
V S
D E