Pixel Repetition - Analog Devices ADV8003 Hardware Manual

dcfifo_kill_dis, HDMI RX Map, Address 0xE21B[2]
This bit sets the Video FIFO output to zero if there is more than one resynchronization of the pointers within 2 FIFO cycles. This
behavior can be disabled with this bit.
Function
dcfifo_kill_dis
0 
1
dcfifo_kill_not_locked, HDMI RX Map, Address 0xE21B[3]
This bit controls whether or not the output of the Video FIFO is set to zero when the video PLL is unlocked.
Function
dcfifo_kill_not_locked
0
1 
The DCFIFO is programmed to reset itself automatically when the video PLL transitions from unlocked to locked. Note that the video
PLL transition does not necessarily indicate that the overall system is stable.
dcfifo_reset_on_lock, HDMI RX Map, Address 0xE21B[4]
This bit enables the reset/re-centering of video FIFO on video PLL unlock.
Function
dcfifo_reset_on_lock
0
1 

5.7. PIXEL REPETITION

In HDMI mode, video formats with TMDS rates below 25 Mpixels/s require pixel repetition in order to be transmitted over the serial
video link. When the ADV8003 receives this type of video format, it discards repeated pixel data automatically, based on the pixel
repetition field available in the AVI InfoFrame.
When hdmi_pixel_repetition[3:0]
hdmi_pixel_repetition + 1.
hdmi_pixel_repetition[3:0], HDMI RX Map, Address 0xE205[3:0] (Read Only)
This is a readback signal to indicate the current HDMI pixel repetition value decoded from the AVI InfoFrame received. The HDMI Rx
automatically discards repeated pixel data and divides the pixel clock frequency appropriately as per the pixel repetition value.
Rev. B, August 2013
Description
FIFO output set to zero if more than one resynchronization is necessary during two FIFO
cycles
FIFO output never set to zero regardless of how many resynchronizations occur
Description
FIFO data is output regardless of video PLL lock status
FIFO output is zeroed if video PLL is unlocked
Description
Do not reset on video PLL lock
Reset FIFO on video PLL lock
is non zero, video pixel data is discarded and the pixel clock frequency is divided by
232
ADV8003 Hardware Manual