Automatic Contrast Enhancement; Secondary Vsp; Introduction To Svsp; Figure 60: Adv8003 Svsp - Analog Devices ADV8003 Hardware Manual

The input video to the PtoI block is defined using m_p2i_vid[7:0]. Refer to
m_p2i_vid[7:0], Secondary VSP Map, Address 0xE64B[7:0]
'This register is used to set the VIC of the PtoI in VSP_top.
Function
m_p2i_vid[7:0]
0x00 
The PVSP PtoI does not have direct access to the data from the input pins but it can be utilized to convert a progressive input format to
interlaced using the PVSP core bypass path by setting the
3.2.3.16.

Automatic Contrast Enhancement

The Automatic Contrast Enhancement (ACE) block is used to intelligently enhance the contrast of the whole picture by making dark
regions darker and bright regions brighter. It is stable under scene changes as well as being robust in the presence of noise. ACE
supports both interlaced and progressive inputs and can be enabled/disabled using ace_enable.
ace_enable, IO Map, Address 0x1A30[7]
This bit is used to enable the automatic contrast enhancement (ACE) block.
Function
ace_enable
0 
1

3.3. SECONDARY VSP

3.3.1.

Introduction to SVSP

Secondary VSP Secondary VSP
Input Input
Video Video
Figure 60 shows the structure of the
PtoI converter.
Rev. B, August 2013
Description
Default

Table 30: VID Set to PtoI

Input Timing Format to
P2I
svsp_m_p2i_vid
pvsp_bypass
Description
Bypass A.C.E.
Enable A.C.E.
FFS FFS
VIM VIM
Write to Write to
DDR2 DDR2

Figure 60: ADV8003 SVSP

SVSP. The SVSP comprises of four sections; the VIM, the VOM, a controller which is the FFS, and a
Table 30 for more details on the value of this register.
576p 1080p50 480p
17 31 2
bit.
VOM VOM
Read from Read from
DDR2 DDR2
180
ADV8003 Hardware Manual
1080p60
16
Output Output
Video Video
Progressive Progressive
to Interlaced to Interlaced