Frame Tracking - Analog Devices ADV8003 Hardware Manual

svsp_vid_clk_update, IO Map, Address 0x1A3F[4]
This bit is used to trigger the open loop period to be captured in the DPLL. A low to high transition triggers the action.
Function
svsp_vid_clk_update
0 
1
For example, the following procedure for updating the SVSP DPLL clock period is very similar to that of the PVSP:
1A 1A39 0A – Put the DPLL into ADV8003 mode
1A 1A40 XX – Configure DPLL clock period setting
1A 1A41 XX – Configure DPLL clock period setting
1A 1A42 XX – Configure DPLL clock period setting
1A 1A43 XX – Configure DPLL clock period setting
1A 1A3F 80 – Recommended setting
1A 1A3F 90 – Recommended setting
Once configured, the clock in

2.2.4.3. Frame Tracking

The ADV8003 employs frame tracking on its scaler outputs. There will always be some error in the input frame rate versus the ideal frame
rate. This could cause frame drops or repeats at the output. Frame tracking allows the output timing to track the input timing in such a
way that eliminates frame drops and repeats while also remaining immune to discontinuities in the input. The system can be fully
frequency and phase locked using pvsp_err_sel. If phase locked is selected, there will be an integer frame latency from input to output. If
frequency locked is selected, there could be a non integer frame latency number from input to the output. Selecting phase error latency is
the recommended setting.
pvsp_err_sel, IO Map, Address 0x1A4EH
This bit is used to choose between phase locked loop and frequency locked loop for the Primary VSP frame tracking mode.
Function
pvsp_err_sel
0 
1
svsp_err_sel, IO Map, Address 1A4FH
This bit is used to choose between phase locked loop and frequency locked loop for the Secondary VSP frame tracking mode.
Function
svsp_err_sel
0 
1
Frame tracking results in an integer ratio relationship between the input and output frame rates of 1:1, 2:1, 1:2, 5:2 or 2:5. For example, if
scaling from 1080p30 to 720p59.94 with frame tracking enabled, the resulting output may be 720p60 due to the 1:2 relationship.
Frame rate tracking is primarily intended for cases where the input frame rate and output frame rate have a 1:1 relationship or are close to
this target, that is, 59.94 Hz to 60 Hz. However, it can also be used for some standard frame rate conversion modes such as 24 Hz to 60
Hz, 25 Hz to 50 Hz, and 30 Hz to 60 Hz. The list of scaling conversions where frame tracking can be enabled is covered in
Rev. B, August 2013
Description
Do not update open_loop_period in DPLL
Update open_loop_period in DPLL
Figure 41 is programmed for operation.
Description
Phase error
Frequency error
Description
Phase error
Frequency error
112
ADV8003 Hardware Manual
Table 9.