Figure 41: Pvsp/Svsp Output Clock Configure; Table 8: Example Values For Dpll_Clock_Period - Analog Devices ADV8003 Hardware Manual

For the PVSP and SVSP, the correct clocks must be configured manually. This can be done using the DPLL period registers, which allows
the user to program the sampling rate for the appropriate output format by I
Equation 1.
Once the dpll_phase_period is calculated,
where output_clock_period is the period of the desired output sampling frequency.
For example, for HD video, the output clock sampling frequency would be 148.5 MHz. This equation returns a decimal value. Once
calculated, this should be converted to hex and written to
some common resolutions and their associated dpll_clock_period values.
Active Resolution
720 x 480i
720 x 480p
720 x 576i
720 x 576p
960 x 480i
960 x 576i
1280 x 720p
1280 x 720p
1920 x 1080i
1920 x 1080i
1920 x 1080p
1920 x 1080p
1920 x 1080i
Rev. B, August 2013
Secondary Secondary
Secondary VSP Secondary VSP

Figure 41: PVSP/SVSP Output Clock Configure

dpll _ phase _ period
Equation 1: Calculating DPLL Phase Period
Equation 2 is used to calculate the dpll_clock_period.
dpll _ clock _ period
Equation 2: Calculating DPLL Clock Period
pvsp_vid_clk_period[33:0]

Table 8: Example Values for dpll_clock_period

Frame Rate (Hz)
29.97
59.94
25
50
29.97
25
59.94
60
29.97
30
59.94
60
25
Primary Primary
VSP VSP
Primary VSP Primary VSP
dpll clock dpll clock
VSP VSP
dpll clock dpll clock
C. The equation for calculating this I
2
1
≡
× ×
64 12 27 MHz
output _ clock _ period
≡
dpll _ phase _ period
and svsp_vid_clk_period[33:0].
Sampling
Frequency (MHz)
13.5
27
13.5
27
18
18
74.175
74.25
74.175
74.25
148.35
148.5
74.25
110
ADV8003 Hardware Manual
C value is provided in
2
×
22
2
dpll_clock_period
(Hex)
0x180000000
0x0C0000000
0x180000000
0x0C0000000
0x120000000
0x120000000
0x045E386DC
0x045D1745D
0x045E386DC
0x045D1745D
0x022F1C36E
0x022E8BA2F
0x045D1745D
Table 8 outlines