Protocol For Main I C Port; Figure 11: Register Map Architecture; Table 6: Adv8003 I C Address And Register Address Range For Different Hw Blocks - Analog Devices ADV8003 Hardware Manual

1.5. PROTOCOL FOR MAIN I
The system controller initiates a data transfer by establishing a start condition, defined by a high to low transition on SDA while SCL
remains high. This transition indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the
next eight bits (7-bit address and R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the
transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other
devices withdraw from the bus at this point and maintain an idle condition.
In the idle condition, the device monitors the SDA and SCL lines for the start condition and the correct transmitted address. The R/W bit
determines the direction of the data. A logic 0 on the LSB of the first byte means that the master will write information to the peripheral. A
logic 1 on the LSB of the first byte means that the master will read information from the peripheral.
The ADV8003 has a single 8-bit I
through 16-bit addressing and 8-bit data registers. The ADV8003 acts as a standard slave device on the I
as the I 2 C address and the second byte and third bytes as the appropriate subaddress. The fourth byte is then considered the data for this
subaddress register. This means that I
For example, to write 0xFF to the encoder register map, register 0x59AF, the I
are outlined in Table 6. Figure 11
Register Map Name
IO Map
Primary VSP Map
Primary VSP Map 2
Secondary VSP Map
Rx Main Map
Rx InfoFrame Map
Tx1 Main Map
Tx1 EDID Map
Tx1 CEC Map
Tx1 UDP Map
Tx1 Test Map
Tx2 Main Map
Tx2 EDID Map
Tx2 CEC Map
Tx2 UDP Map
Tx2 Test Map
Encoder Map
DPLL Map
IO
MAP
2
I C
0x1A00 TO
ADDRESS
0x1BFF
0x18/0x1A
SCL
SDA
0xEC00 TO
0xECFF
Tx1 MAIN
MAP
Rev. B, August 2013
C PORT
2
C slave address. All register maps within the ADV8003 can be accessed through this I
2
2 C writes to the part will be in the form <I
shows the register map architecture for the ADV8003.
Table 6: ADV8003 I C Address and Register Address Range for Different HW Blocks
2
PRIMARY VSP PRIMARY VSP
MAP MAP 2
0xE800 TO 0xE900 TO
0xE8FF 0xE9FF
0xEE00 TO 0xF000 TO
0xEEFF 0xF0FF
Tx1 EDID Tx1 CEC
MAP MAP

Figure 11: Register Map Architecture

2 C Address>, <Address MSBs>, <Address LSBs>, <Data>.
C writes needed are 0x1A, 0x59, 0xAF, 0xFF. The addresses
2
I 2 C Address
0x1A (0x18 with LSB low)
SECONDARY DPLL
VSP MAP MAP
0xE600 TO 0xE000 TO
0xE6FF 0xE0FF
0xF200 TO 0xF400 TO
0xF2FF 0xF4FF
Tx1 UDP Tx2 MAIN
MAP MAP
67
C bus. It interprets the first byte
2
Register Address
0x1A00 to 0x1BFF
0xE800 to 0xE8FF
0xE900 to 0xE9FF
0xE600 to 0xE6FF
0xE200 to 0xE2FF
0xE300 to 0xE3FF
0xEC00 to 0xECFF
0xEE00 to 0xEEFF
0xF000 to 0xF0FF
0xF200 to 0xF2FF
0xF300 to 0xF3FF
0xF400 to 0xF4FF
0xF600 to 0xF6FF
0xF800 to 0xF8FF
0xFA00 to 0xFAFF
0xFB00 to 0xFBFF
0xE400 to 0xE4FF
0xE000 to 0xE0FF
Rx MAIN Rx INFOFRAME
MAP MAP
0xE200 TO 0xE300 TO
0xE2FF 0xE3FF
0xF600 TO 0xF800 TO
0xF6FF 0xF8FF
Tx2 EDID Tx2 CEC
MAP MAP
ADV8003 Hardware Manual
C address
2
ENCODER Tx1 TEST
MAP MAP
0xE400 TO 0xF300 TO
0xE4FF 0xF3FF
0xFA00 TO 0xFB00 TO
0xFAFF 0xFBFF
Tx2 UDP Tx2 TEST
MAP MAP