Figure 38: Ddr Mode, Luma And Chroma Swap - Analog Devices ADV8003 Hardware Manual

Function
exosd_format_sel[4:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C 
exosd_swap_bus_ctrl[2:0], IO Map, Address 0x1B68[7:5]
This signal is used to control the external OSD input pixel bus. The input pixel bus is 24 bits wide and is divided into three data
channels: Top = D[23:16], Middle = D[15:8] and Bottom = D[7:0]. This register allows the user to swap the order of these three data
channels.
Function
exosd_swap_bus_ctrl[2:
0]
000 
001
010
011
100
101
110
111
The input formatter also has a number of controls which can be used to provide extra flexibility in terms of data processing.
Once a DDR mode is selected using exosd_format_sel[4:0], the order of the luma and chroma data can be configured using
exosd_ddr_yc_swap. In DDR modes, the luma is expected on the rising edge of the pixel clock. Setting this bit to 1 swaps the luma and
chroma samples and places the chroma sample (C) on the rising edge and the luma sample (Y) on the falling edge. Refer to
more information. The edge on which each sample of DDR data is latched into the part can be specified using exosd_ddr_edge_sel.
exosd_ddr_yc_swap, IO Map, Address 0x1B6A[0]
This bit is used to swap the Luma (Y) and Chroma (C) data in DDR modes. By default, Y is expected on the rising edge of the clock.
Rev. B, August 2013
Description
1 x 8 bit bus 4:2:2
1 x 10 bit bus 4:2:2
1 x 12 bit bus 4:2:2
2 x 8 bit buses 4:2:2
2 x 10 bit buses 4:2:2
2 x 12 bit buses 4:2:2
3 x 8-bit buses, SDR 4:4:4
3 x 10-bit buses, SDR 4:4:4
3 x 12-bit buses, SDR 4:4:4
1 x 8 bit DDR bus 4:2:2
1 x 10 bit DDR bus 4:2:2
1 x 12 bit DDR bus 4:2:2
3 x 8 bit buses 4:4:4
Description
D[23:16] D[15:8] D[7:0]
D[23:16] D[7:0] D[15:8]
D[23:16] D[15:8] D[7:0]
D[15:8] D[23:16] D[7:0]
D[7:0] D[23:16] D[15:8]
D[7:0] D[15:8] D[23:16]
D[15:8] D[7:0] D[23:16]
D[23:16] D[15:8] D[7:0]
Y Y C C Y Y C C Y Y
C C Y Y C C Y Y C C

Figure 38: DDR Mode, Luma and Chroma Swap

C C Y Y C C ddr_yc_swap = 0 ddr_yc_swap = 0
Y Y C C Y Y ddr_yc_swap = 1 ddr_yc_swap = 1
101
ADV8003 Hardware Manual
Figure 34 for