General Digital Inputs And Outputs; Xtal And Load Cap Value Selection; Figure 138: Crystal Circuit; Table 94: Recommended Psu Decoupling For Adv8003-8 Parts - Analog Devices ADV8003 Hardware Manual

PSU
AVDD3
PVDD5
PVDD6

General Digital Inputs and Outputs

The trace length that the digital inputs/outputs have to sink/source should be minimized. Longer traces have higher capacitance, which
requires more current that can cause more internal digital noise. Shorter traces reduce the possibility of reflections. It is recommended to
route traces in the shortest trace length possible and keep the number of layer transitions to a minimum.
If possible, the digital output driver capacitance loading should be limited to less than 15 pF. This can be accomplished easily by keeping
traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current
transients inside the ADV8003, creating more digital noise on its power supplies.
Particular attention must be paid to the routing of clock and sync signals, for example, PCLK, OSD_CLK, HS, OSD_HS, VS, OSD_VS,
DE, OSD_DE, XTALN, and XTALP. Any noise that gets onto these signals can add jitter to the system. Therefore, the trace length should
be minimized, and digital or other high frequency traces should not be run near it.

XTAL and Load Cap Value Selection

The ADV8003 requires a 27 MHz crystal.
taken when using a crystal circuit to generate the reference clock for the ADV8003. Small variations in reference clock frequency can
impair the performance of the ADV8003.
These guidelines are followed to ensure correct operation:
• Use the correct frequency crystal (27 MHz recommended). Tolerance should be 50 ppm or better.
•
Know the C for the crystal part number selected. The value of capacitors C1 and C2 must be matched to the C
load
specific crystal part number in the user's system.
Rev. B, August 2013

Table 94: Recommended PSU Decoupling for ADV8003-8 Parts

Ball Number Capacitance Required
G23 4 x 100nF
G23 1 x 10nF
N22 3 x 100nF
N22 1 x 10nF
W22 3 x 100nF
W22 1 x 10nF
n/a 10uF
M21 2 x 100nF
M21 1 x 10nF
N21 2 x 100nF
N21 1 x 10nF
n/a 10uF
V21 2 x 100nF
V21 1 x 10nF
W21 2 x 100nF
W21 1 x 10nF
n/a 10uF
Figure 138 shows an example of a reference clock circuit for the ADV8003. Special care must be
47pF
Placement
As close as possible to ADV8003
As close as possible to ADV8003
As close as possible to ADV8003
As close as possible to ADV8003
As close as possible to ADV8003
As close as possible to ADV8003
Place on AVDD3 trace after the EMC filter
As close as possible to ADV8003
As close as possible to ADV8003
As close as possible to ADV8003
As close as possible to ADV8003
Place on PVDD5 trace after the EMC filter
As close as possible to ADV8003
As close as possible to ADV8003
As close as possible to ADV8003
As close as possible to ADV8003
Place on PVDD5 trace after the EMC filter
X T A L
27MHz
C1
C2
47pF

Figure 138: Crystal Circuit

360
ADV8003 Hardware Manual
for the
load