Autoconfiguration; Table 22: Pvsp Supported Input Video Timing And Vid - Analog Devices ADV8003 Hardware Manual

Function
pvsp_enable_ffs
0 
1

3.2.1.1. Autoconfiguration

Each block inside VIM and VOM can be automatically configured to reduce the configuration complexity. Two registers,
pvsp_autocfg_input_vid[7:0]
The 59.94/23.97 Hz timings have the same VID as the corresponding 60/24Hz timing in
pvsp_autocfg_input_vid[7:0], Primary VSP Map, Address 0xE881[7:0]
This register is used to set the input timing VIC. If this register is 0, PVSP will use values in registers of pvsp_vin_h, pvsp_vin_v,
pvsp_is_i_to_p and pvsp_vin_fr to set input video.
Function
pvsp_autocfg_input_vi
d[7:0]
0x06 
0xXX
Rev. B, August 2013
Description
Disable FFS/FRC
Enable FFS/FRC
and pvsp_autocfg_output_vid[7:0]
Description
Default: 480i@60
Input timing VID

Table 22: PVSP Supported Input Video Timing and VID

Video Timing
640x480p60
720x480p60
720x240p60
1280x720p60
1920x1080i60
720x480i60
1920x1080p
720x576p50
1280x720p50
1920x1080i50
720x576i50
720x288p50
1920x1080p50
CEA
1920x1080p24
1920x1080p25
1920x1080p30
1080i50-even
1080i100
720p100
576p100
576i100
1080i120
720p120
480p120
480i120
576p200
576i200
should be set to make the autoconfiguration work.
Figure
VID
1
2 or 3 or 14 or 15 or 35 or 36
8 or 9 or 12 or 13
4
5
6 or 7 or 10 or 11
16
17 or 18 or 29 or 30 or 37 or 38
19
20
21 or 22 or 25 or 26
23 or 24 or 27 or 28
31
32
33
34
39
40
41
42 or 43
44 or 45
46
47
48 or 49
50 or 51
52 or 53
54 or 55
146
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